Browse Prior Art Database

Low Power Substrate Voltage Generator

IP.com Disclosure Number: IPCOM000060730D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Ellis, WF: AUTHOR [+2]

Abstract

Multiple, low power substrate voltage (Vsub) generators, when placed at the corners of a large chip, provide uniform substrate voltage distribution. A decrease in power consumption is achieved by using low Vt enhancement transistors in the pump drivers. The low power Vsub generator circuit, shown in the figure, is comprised of an oscillator 20, a charge pump driver (transistors 1, 2, 3, 4, 11, 12) and a charge pump (transistors 5-10). One of these circuits is provided on each corner of the chip. This results in more stability and uniformity in the overall voltage supplied to the chip. When the output from the oscillator 20 rises, nodes N1 and N2 are pulled to ground potential through transistors 12 and 2, respectively, turning transistors 4, 6, and 11 off.

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Low Power Substrate Voltage Generator

Multiple, low power substrate voltage (Vsub) generators, when placed at the corners of a large chip, provide uniform substrate voltage distribution. A decrease in power consumption is achieved by using low Vt enhancement transistors in the pump drivers. The low power Vsub generator circuit, shown in the figure, is comprised of an oscillator 20, a charge pump driver (transistors 1, 2, 3, 4, 11, 12) and a charge pump (transistors 5-10). One of these circuits is provided on each corner of the chip. This results in more stability and uniformity in the overall voltage supplied to the chip. When the output from the oscillator 20 rises, nodes N1 and N2 are pulled to ground potential through transistors 12 and 2, respectively, turning transistors 4, 6, and 11 off. With transistor 11 off, no current flows from VH to ground through transistors 11 and 12. Node N3 is pulled to a voltage VH through transistor 3. Node N3 then turns on transistor 5 to charge C1 to a voltage level of VH minus a threshold voltage Vt. Node N6 couples up through transistor 9to turn transistor 8 on, such that node N5 can be pulled down to ground, leaving capacitor C1 charged. When the output from oscillator 20 falls, transistors 2 and 12 turn off, pulling node N2 to VH through transistor 1. Transistor 11 turns on, charging node N1 to Vt below Vdd. This prevents any current from flowing from VH to ground through transistors 5 and 6. As node N1 rises, transistor 6...