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Mechanism for the Implementation of Alternate Input-Output Architecture on an IBM Series/1 Processor

IP.com Disclosure Number: IPCOM000060757D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 49K

Publishing Venue

IBM

Related People

Newmark, CA: AUTHOR [+4]

Abstract

This article describes a technique which allows existing IBM Series/1 operating systems and applications to make use of non-IBM Series/1 Input/Output (I/O) devices without modification of I/O device-dependent IBM Series/1 software. The technique disclosed herein is based on an alternative to the definition of the IBM Series/1 operate Input/Output I/O instruction as set forth in the reference [*]. The alternative described by this article allows for support of non-IBM Series/1 I/O devices driven by unmodified I/O device-dependent IBM Series/1 software.

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Mechanism for the Implementation of Alternate Input-Output Architecture on an IBM Series/1 Processor

This article describes a technique which allows existing IBM Series/1 operating systems and applications to make use of non-IBM Series/1 Input/Output (I/O) devices without modification of I/O device-dependent IBM Series/1 software. The technique disclosed herein is based on an alternative to the definition of the IBM Series/1 operate Input/Output I/O instruction as set forth in the reference [*]. The alternative described by this article allows for support of non-IBM Series/1 I/O devices driven by unmodified I/O device-dependent IBM Series/1 software. The operate I/O instruction is modified to perform a class interrupt in a similar manner to the supervisor call instruction using the previously reserved storage locations X'0028' and X'002A' as the level status block pointer and the start instruction address, respectively (see chart for storage allocation after power-on-reset). This allows for an orderly interception of the I/O instructions appearing in I/O device-dependent IBM Series/1 software. Once the operate I/O instruction has been intercepted in this manner, a new code module (whose entry point is the start instruction address) added to the operating system is responsible for decoding the operate I/O instruction and performing the function appropriate to the new I/O architecture supported by this new code module. This new code module is capable of supporting memory-mapped I/O or of redefining the usage of existing I/O instructions substituting the newly architected read I/O and write I/O instructions. The read I/O and write I/O instructions also allow the new code module to continue to support the existing IBM Series/1 I/O architecture. Since additional instructions are required, this function will not be seen as a feature of standard IBM Series/1 processors.

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The instruction address register is incremented by two. Alevel status block (LSB) is stored, starting at the main storage location specified by the contents of the Operate I/O LSB pointer, at main storage location 0028 hexadecimal using an address key of zero. The summary mask (interrupts) is disabled. The trace bit is turned Off. The equate operand space bit is turned Off. The contents of OP2K are loaded into OP1K; then, OP2K and ISK are set to zero. The indicators are unchanged. Bits 8-15 of the instruction are loaded into the low-order byte of register 1. The high-order byte of register 1 is set to zero. Subsequently, the contents of main storage location 002A hexadecimal, address key zero (Operate I/O start instruction address SIA), are loaded into the instruction address register, becoming the address of the next instruction to be fetched.

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Data is read from the selected I/O facility to storage (to the immediate data field of the IDCB). The Address field is added to the contents of the register specified by the R2 field to form an effec...