Browse Prior Art Database

Buffered Direct Drive NMOS Logic Design

IP.com Disclosure Number: IPCOM000060762D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Reynolds, CB: AUTHOR

Abstract

Buffered direct drive (BDD) is achieved by using an appropriate configuration of enhancement-mode transistors gated with the circuit's input signals as pull-ups for a post-driver output stage. BDD can be used for any general logic function. Compared to conventional non- inverting NMOS logic having push-pull output inverter stages, the BDD approach results in lower power dissipation and less circuit delay. The circuit shown contains the standard NMOS OR-AND-invert gate comprised of transistors 1-5. It has the logic function: 20 = (A0+B0) x (A1+B1) Transistors 6-9, having topology identical to transistors 1-4, are used as pull-ups for a post-driver output stage. The gate of transistor 12 is pulled up and down more rapidly than if standard depletion device current source pull-up is used.

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Buffered Direct Drive NMOS Logic Design

Buffered direct drive (BDD) is achieved by using an appropriate configuration of enhancement-mode transistors gated with the circuit's input signals as pull-ups for a post-driver output stage. BDD can be used for any general logic function. Compared to conventional non- inverting NMOS logic having push-pull output inverter stages, the BDD approach results in lower power dissipation and less circuit delay. The circuit shown contains the standard NMOS OR-AND-invert gate comprised of transistors 1-5. It has the logic function: 20 = (A0+B0) x (A1+B1) Transistors 6-9, having topology identical to transistors 1-4, are used as pull-ups for a post-driver output stage. The gate of transistor 12 is pulled up and down more rapidly than if standard depletion device current source pull-up is used. Transistors 6-9 do not allow DC current to flow from VDD (+5 volts) to ground through transistor 10 when node 20 is high, thus minimizing circuit power consumption. Transistor 11 serves as the post-driver pull-down device, pulling node 10 low as in the standard case of an NMOS push-pull circuit. Low threshold devices may be substituted for transistors 6-9 to improve circuit performance.

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