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Contactless One-Device Cell With Low Bit-Line Capacitance

IP.com Disclosure Number: IPCOM000060765D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Lee, HS: AUTHOR

Abstract

In this one-device storage cell, one polycrystalline silicon (Poly Si) stripe is used for a bit line BL and one for storage ST. A self- aligned shallow N+ to P junction beneath stripes of the first Poly Si is used for the storage plate and for very high density bit/sense lines. A one-device memory cell, as shown in the figure, includes recessed oxide (ROX) segments, illustrated as horizontal strips located under first level vertical Poly Si lines ST. The remaining first level vertical Poly Si lines are the bit lines BL. Prior to forming these lines, a thin layer of silicon dioxide 4 is doped with an N type impurity.

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Contactless One-Device Cell With Low Bit-Line Capacitance

In this one-device storage cell, one polycrystalline silicon (Poly Si) stripe is used for a bit line BL and one for storage ST. A self- aligned shallow N+ to P junction beneath stripes of the first Poly Si is used for the storage plate and for very high density bit/sense lines. A one-device memory cell, as shown in the figure, includes recessed oxide (ROX) segments, illustrated as horizontal strips located under first level vertical Poly Si lines ST. The remaining first level vertical Poly Si lines are the bit lines BL. Prior to forming these lines, a thin layer of silicon dioxide 4 is doped with an N type impurity. After lines BL and ST are formed by etching to the substrate 6surface, the impurity in the silicon dioxide is driven into the substrate 6 to form the self-aligned, shallow N+ layer 8, as indicated in the sectional view (sec. A-A). The shaded portion of the plan view, defined by the width of a line ST between ROX segments ROX1 and ROX2, outlines the area of the storage capacitor SC. As also shown, adjacent bit lines BL have ROX arranged between them which is spaced from the edge of each bit line BL. The word line WL is a second layer of Poly Si arranged orthogonal to lines BL and ST over an insulating layer. The process sequence is as follows: 1) ROX mask. 2) Blanket implant arsenic (As) into thin oxide. 3) Delineate first level Poly Si and implanted thin oxide sandwich to define bit lines BL an...