Browse Prior Art Database

Cmos Multi-Way and Logic

IP.com Disclosure Number: IPCOM000060767D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Loehlein, WD: AUTHOR [+2]

Abstract

Proposed is a circuit implementation, by means of which logic circuits with a plurality of inputs may be obtained without (noticeably) impairing the switching speed. This is essentially accomplished by a low- ohmic, sense circuit triggered discharge path which is provided parallel to the input chain. Fig. 1 shows a conventional 4-way AND gate, at whose output a logic "1" occurs if all inputs A, B, C, D are "1". In that state, all (P-channel) transistors T1 to T4 are off, and node A is discharged by series-connected (N-channel) input transistors T5 to T8. As this series connection mainly influences the circuit delay, the number of inputs provided is in most cases limited to, say, four. In the proposed circuit (Fig. 2), two series-connected transistors T5/T6 are provided in parallel to the actual discharge path T2...

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Cmos Multi-Way and Logic

Proposed is a circuit implementation, by means of which logic circuits with a plurality of inputs may be obtained without (noticeably) impairing the switching speed. This is essentially accomplished by a low- ohmic, sense circuit triggered discharge path which is provided parallel to the input chain. Fig. 1 shows a conventional 4-way AND gate, at whose output a logic "1" occurs if all inputs A, B, C, D are "1". In that state, all (P-channel) transistors T1 to T4 are off, and node A is discharged by series-connected (N-channel) input transistors T5 to T8. As this series connection mainly influences the circuit delay, the number of inputs provided is in most cases limited to, say, four. In the proposed circuit (Fig. 2), two series-connected transistors T5/T6 are provided in parallel to the actual discharge path T2...Tx (consisting of, say, eight series-connected transistors). To that end, transistor T6 is fully switched on if the output potential is zero (AND function not fulfilled). If all inputs are "1", node A is initially discharged slowly through T2 ...Tx. The amplifier T7/T8 at node A is unsymmetrically dimensioned,
i.e., T7 is very large, whereas T8 is very small. Hence, if the potential at node A drops only slightly, transistor T5 is turned on through T7, and node A is discharged across the relatively low-ohmic parallel path T5/T6. As soon as the output level goes up ("1"), the small-dimension inverter stage T9/T10 blocks transistor...