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Variable CRT Dot Widths From a Constant Frequency

IP.com Disclosure Number: IPCOM000060768D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Fawcett, BW: AUTHOR

Abstract

The capability of changing the stroke widths of its characters without changing the video dot frequency and to dynamically vary the amount of change is given to a CRT terminal. This is done by changing the widths of either the first or the last dot in each scan line of each character stroke. The first dot can be shrunk, or the last dot can be stretched. The amount the dot width is changed can be adjusted on a character, row, or screen basis by the display adapter hardware and/or a microprocessor writable register. For stroke shrinking the dots making up the horizontal character slice come out of the character generator ROM (read-only memory) 1 and are loaded into a parallel-to-serial register or dot serializer 2.

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Variable CRT Dot Widths From a Constant Frequency

The capability of changing the stroke widths of its characters without changing the video dot frequency and to dynamically vary the amount of change is given to a CRT terminal. This is done by changing the widths of either the first or the last dot in each scan line of each character stroke. The first dot can be shrunk, or the last dot can be stretched. The amount the dot width is changed can be adjusted on a character, row, or screen basis by the display adapter hardware and/or a microprocessor writable register. For stroke shrinking the dots making up the horizontal character slice come out of the character generator ROM (read-only memory) 1 and are loaded into a parallel-to-serial register or dot serializer 2. The serial video dot stream on line 3 is then sent to two places: to the dot shrinking "AND" gate 4 and to delay generator 5. Delay generator 5 leaves the video waveform intact but just delays it a certain amount. The amount of delay is controlled by a microprocessor register 7 and/or video system logic 8. Different delays are produced by selector 9 which selects one of the outputs from delay generator 5. The delayed and raw video signals on lines 10 and 3, respectively, meet at the dot shrinker "AND" gate 4 and are ANDed together to produce a chopped signal on line 11. These signals are shown in Fig. 2. The falling edge stays the same, but the rising edge shifts out the amount of the delay. This produces...