Browse Prior Art Database

Floating-Point Unit Cycle Generator

IP.com Disclosure Number: IPCOM000060770D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Genduso, TB: AUTHOR [+3]

Abstract

A technique is described whereby a computer program, called floating- point unit cycle time generator, utilizes a set of programming functions to create timing diagrams of floating-point operating instructions. The program is particularly useful in assessing the design and performance of a system of pipelined processors, operating concurrently, eliminating the need to develop simulator programs. With the advent of parallel processing and the use of pipelining to perform computer processing, the ability to predict the processing speed of computers, prior to hardware implementation, has been difficult because of the variables in the efficient use and the lack of analytical techniques of the elements involved. A typical technique is to study the performance of systems through the use of simulation models.

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Floating-Point Unit Cycle Generator

A technique is described whereby a computer program, called floating- point unit cycle time generator, utilizes a set of programming functions to create timing diagrams of floating-point operating instructions. The program is particularly useful in assessing the design and performance of a system of pipelined processors, operating concurrently, eliminating the need to develop simulator programs. With the advent of parallel processing and the use of pipelining to perform computer processing, the ability to predict the processing speed of computers, prior to hardware implementation, has been difficult because of the variables in the efficient use and the lack of analytical techniques of the elements involved. A typical technique is to study the performance of systems through the use of simulation models. Unfortunately, simulation models tend to be large, require a long running time and are difficult to vary the operational parameters. Queuing models and other conventional analytical tools are also used; however, they do not provide the required level of detail needed for system development. As a result, the floating-point unit cycle time generator was developed so that cycle timing charts, from the actual workload requirements, are made available prior to implementation into hardware. Design alternatives may be evaluated by changing values in a cycle time matrix. The timing charts provide a visualization of instruction sequences showing the degree of overlap achieved in the floating- point unit. Floating-point analysis was previously performed from manually developed charts, called FDEAT charts. The FDEAT is derived from the cycle sequence "fetch, decode, execute, address and transfer." The FDEAT charts were used in the analysis of generating cycle counts for floating-point kernels. This was a laborious process. As a result, machine-generated cycle timing diagrams were developed. Floati...