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High-Speed Processor Bus Arbitration

IP.com Disclosure Number: IPCOM000060773D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 58K

Publishing Venue

IBM

Related People

Finney, DW: AUTHOR [+4]

Abstract

This article describes a highly efficient arbitration scheme for resolving contention between bus units that have the capability of functioning as bus masters on a common bus in order to access shared resources, such as memory units. Bus units that have the ability to take temporary control of the bus are referred to here as bus master units (BMUs). In a given system the BMUs may include one or more processing units (PUs) and several I/O interfacing points, or other specialized functional units, such as a floating-point unit, all of which share a common processor bus for accessing shared memory or I/O devices. Fig. 1 illustrates in block diagram the relation between BMUs, the processor bus, and a bus arbiter.

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High-Speed Processor Bus Arbitration

This article describes a highly efficient arbitration scheme for resolving contention between bus units that have the capability of functioning as bus masters on a common bus in order to access shared resources, such as memory units. Bus units that have the ability to take temporary control of the bus are referred to here as bus master units (BMUs). In a given system the BMUs may include one or more processing units (PUs) and several I/O interfacing points, or other specialized functional units, such as a floating-point unit, all of which share a common processor bus for accessing shared memory or I/O devices. Fig. 1 illustrates in block diagram the relation between BMUs, the processor bus, and a bus arbiter. It is assumed that the processor bus is also attached to other bus units (not shown) that may be accessed as slave units, e.g., a storage control unit interfacing with shared memory. In Fig. 1, priority level is assumed to be in descending order from BMU 0, which has the highest priority, to BMU 3 which has the lowest priority. In order to initiate a transfer on the processor bus, a BMU must present a request to the bus arbiter to determine when the bus is free for its use. It will signal the arbiter by activating a Bus Request. Each BMU has an individual request line, except for the lowest priority unit, which has a default request, indicated by a dotted line from BMU 3 that is always active and, therefore, requires no special request line. The arbiter will generate acorresponding Bus Grant signal, on a dedicated line, to the requesting unit with highest priority. Note that the BMU having the highest assigned priority does not require a Bus Grant from the arbiter. The Bus Request signal can simply be tied to the Bus Grant input for this unit, as shown in Fig. 1 for BMU 0, or the grant can be automatically assumed by the internal logic of the bus unit, thus saving the use of a pin. Another signal shown in Fig. 1, Bus Busy, is used to control the timing of a "bus capture", i.e., the point at which a new bus master, that has received a Bus Grant signal, can actually take control of the bus to initiate a transfer. The use of this signal increases the efficiency of the arbitration process by allowing arbitration to proceed in parallel with the completion of an operation by a lower priority BMU. When the current bus master is ready to relinquish the bus, it drops Bus Busy. At this point the bus becomes available to any BMU, of higher or lower priority, that has received a Bus Grant. If Bus Busy is active when a BMU receives a grant, the unit must sample its Bus Grant again in the next cycle to ensure that the arbiter has not granted the bus to a higher priority unit. Arbitration is effected on a cycle-by-cycle basis. To simplify the logic of the arbiter, requests are latched in the requesting units, so that no latches or other memory elements are required in the arbiter. Arbiter prioritization...