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Pipeline Control Structure for Processor Unit

IP.com Disclosure Number: IPCOM000060775D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 63K

Publishing Venue

IBM

Related People

Cannon, JW: AUTHOR [+6]

Abstract

This article describes a pipeline control structure for a processor unit (PU) wherein each chip in the processor unit generates its own controls internally. Cycle time is reduced because delays due to controls having to cross chip boundaries are eliminated and successive control registers are in close proximity. I/O pins on the chip previously required for controls are free for other needed functions. In the present disclosure a four-stage pipeline control structure is utilized. In implementing this control structure, each chip in the PU will provide most of its own controls internally. Each chip contains a series of control registers and control logic, each controlling a different phase of instruction execution and the hardware registers used in that phase of execution.

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Pipeline Control Structure for Processor Unit

This article describes a pipeline control structure for a processor unit (PU) wherein each chip in the processor unit generates its own controls internally. Cycle time is reduced because delays due to controls having to cross chip boundaries are eliminated and successive control registers are in close proximity. I/O pins on the chip previously required for controls are free for other needed functions. In the present disclosure a four-stage pipeline control structure is utilized. In implementing this control structure, each chip in the PU will provide most of its own controls internally. Each chip contains a series of control registers and control logic, each controlling a different phase of instruction execution and the hardware registers used in that phase of execution. The exact format of each control register is different for each chip since each chip performs different functions. However, every control register contains a valid bit which indicates whether or not that control register contains valid instruction data. Each valid bit is either set or reset from cycle controls and the previous control register. Fig. 1 illustrates the general control structure of the PU, and Fig. 2 shows the control register timing. Each chip in the PU contains some or all of the control registers as follows: OERead Cycle B Control Register (RCBCR) - the next instruction to be executed is loaded at time "A" (Fig. 2) from the Address/Data (A/D) bus. OEExecute Cycle A Control Register (ECACR) - loaded at time "B" from the RCBCR either directly or gated through logic. OEExecute Cycle B Control Register (ECBCR) - loaded at time "A" from the ECACR either directly or gated through logic. OEWrite Cycle A Control Register (WCACR) - loaded at time "B" from the ECBCR either directly or gated through logic. OEWrite Cycle B Control Register (WCBCR) - loaded at time "A" from the Write Cycle A Control Register either directly or gated through logic. An example of how a subset of these control registers is utilized in the arithmetic logic unit (ALU) chip in the PU to implement this pipeline control structure is discussed below. The ALU chip of the PU performs the arithmetic, logical, and mask/ shift operations. The ALU chip is illustrated in Fig. 3 in block diagram and contains the following functional blocks: B register, data alignment logic, A multiplexer, B multiplexer, barrel shifter, MQ L1 register, MQ L2 register, P and G registers, mask generator, 34-bit ALU with carry lookahead, Z register, condition register, rotate count control register, three control registers, and some control logic. The three control registers utilized in the ALU chip are the RCBCR, ECACR and the ECBCR. The RCBCR is 32 bits wide plus a valid bit. The ECACR is 30 bits wide plus a valid bit. The ECBCR is 19 bits wide plus a valid bit. Only necessary information is passed on from one control register to the next control register. As a resul...