Browse Prior Art Database

Time Sharing of System Data Bus During Storage Head Cycles

IP.com Disclosure Number: IPCOM000060787D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Concha, FF: AUTHOR [+4]

Abstract

This article describes a time sharing of a system data bus during storage read cycles which reduces system data bus utilization and increases processor performance by doing two operations in the time normally required to do one operation. In computer systems, there is frequently an interconnection of various units of the system by the use of common addresses and data busses. To transfer information between the various units of the system, there is usually a well-defined set of sequences involving control signals, the address bus, and the data bus to determine which unit will get control of the busses next and how the information will be transmitted. In many cases the busses between the units are highly utilized and may become a bottleneck that limits the overall system performance.

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Time Sharing of System Data Bus During Storage Head Cycles

This article describes a time sharing of a system data bus during storage read cycles which reduces system data bus utilization and increases processor performance by doing two operations in the time normally required to do one operation. In computer systems, there is frequently an interconnection of various units of the system by the use of common addresses and data busses. To transfer information between the various units of the system, there is usually a well-defined set of sequences involving control signals, the address bus, and the data bus to determine which unit will get control of the busses next and how the information will be transmitted. In many cases the busses between the units are highly utilized and may become a bottleneck that limits the overall system performance. The drawing in block diagram shows one such system in which there is high bus utilization. The technique disclosed herein may be applied to various parts of the system whenever there is need to transfer a block of data (such as instructions, STATUS, or a block move) from storage to one of the units in the system or from unit to unit without an address. The data management unit does error correction code (ECC) checking and generation for main storage data and puts the data into main storage during write operations or on the system data bus during read operations. It also contains hardware buffer registers since it is possible to read several words of data from main storage, but it can only transfer one word of data on the system data bus. The present technique requires three or more signals which are defined as follows: Signal A goes from the storage control unit to the data management unit and is active when a main storage read access is underway. Signal B goes from the processor unit to the data management unit and is active when there is a register in the processor unit available to receive data (an instruction). Signal C goes from the data management unit to the processor unit to clock data from the system data bus into the processor register. In a normal read operation, a request for data from the main storage is made by the processor, co-processor-translator, or the channel bus control unit by first requesting the use of the system address and data busses. When the use of the bus is granted, the unit requesting the data from storage puts the address of the data on the system address bus, makes the r...