Browse Prior Art Database

Threshold-Triggered Filter

IP.com Disclosure Number: IPCOM000060794D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Boyd, JB: AUTHOR [+3]

Abstract

Both amplitude and time domain qualification of read data which is received from a "pit per bit" optical disk read channel is provided. Read signal 10 is shown in the timing diagram of Fig. 1. Each positive peak of this signal represents a data bit read from an optical data disk. This signal is differentiated (20) so that the data is now carried by the zero crossing of signal 20. Referring to Fig. 2, threshold generator 30 generates a voltage 31 which is some fixed percentage of the peak amplitude of signal 20 (Fig. 1). When signal 20 exceeds threshold voltage 31, integrator 40 begins to charge up from alower clamp voltage. If signal 20 is above the threshold for a minimum time interval, then the output of integrator 40 reaches its upper clamp voltage, thereby setting latch 1, which in turn enables latch 2.

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Threshold-Triggered Filter

Both amplitude and time domain qualification of read data which is received from a "pit per bit" optical disk read channel is provided. Read signal 10 is shown in the timing diagram of Fig. 1. Each positive peak of this signal represents a data bit read from an optical data disk. This signal is differentiated (20) so that the data is now carried by the zero crossing of signal 20. Referring to Fig. 2, threshold generator 30 generates a voltage 31 which is some fixed percentage of the peak amplitude of signal 20 (Fig. 1). When signal 20 exceeds threshold voltage 31, integrator 40 begins to charge up from alower clamp voltage. If signal 20 is above the threshold for a minimum time interval, then the output of integrator 40 reaches its upper clamp voltage, thereby setting latch 1, which in turn enables latch 2. The next positive-going transition from zero cross comparator 50 is now qualified as valid data representing a data bit read from the disk. This transition sets latch 2. The output of latch 2 is data pulse 60. Integrator 40 begins to ramp down when signal 20 goes below threshold voltage
31. When the integrator's output voltage reaches the lower clamp, latch 2 is reset, ending data pulse 60. Thus, data pulse width T1 and qualification time T2 are both set by one resistor and one capacitor. The use of latches 1 and 2 prevents comparator chatter from reaching output 60.

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