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Fast Memory Test for Diagnostics

IP.com Disclosure Number: IPCOM000060796D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Scott, SM: AUTHOR

Abstract

This article is a description of the "Fast Memory Test for Diagnostics" algorithm used for performing an exhaustive data test of memory with an Error Correcting Code (ECC) system. This algorithm requires that the memory hardware have the ability to flag the central processor when an uncorrectable error has occurred. The memory is tested by writing a specific set of bit patterns to memory and then reading them back. It is not necessary to compare the bit patterns read back with the bit patterns written to memory. The ECC system will detect an error that it can not correct and flag the central processor. After a segment of memory has been tested, the central processor can test for any errors that occurred within that segment simply by querying the error flag set by the ECC hardware.

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Fast Memory Test for Diagnostics

This article is a description of the "Fast Memory Test for Diagnostics" algorithm used for performing an exhaustive data test of memory with an Error Correcting Code (ECC) system. This algorithm requires that the memory hardware have the ability to flag the central processor when an uncorrectable error has occurred. The memory is tested by writing a specific set of bit patterns to memory and then reading them back. It is not necessary to compare the bit patterns read back with the bit patterns written to memory. The ECC system will detect an error that it can not correct and flag the central processor. After a segment of memory has been tested, the central processor can test for any errors that occurred within that segment simply by querying the error flag set by the ECC hardware. Taking advantage of this results in the main program loop that performs this test being significantly shortened by removing the necessity to compare the data written to memory with the data read back. The algorithm also requires an addressability test and a data path test to be performed before the exhaustive data test mentioned above. The addressability test checks for any of the address lines being grounded, floating or tied together. The data path test checks for any of the data lines being grounded, floating or tied together. These two preliminary tests take an insignificant amount of time to run as compared to the exhaustive data test. The addressability test is performed by writing unique data to a select set of unique addresses and reading them back for verification. The data path test is performed by writing to unique addresses a select set of data and reading them back to verify. The steps of the method are as follows: 1. Test the addressability of the memory to be sure that memory can be uniquely addressed. Refer to segm...