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Cyclic Redundancy Check Code (Crcc) Generating/Checking Logic

IP.com Disclosure Number: IPCOM000060824D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Tran, LT: AUTHOR

Abstract

A technique is described whereby high speed Cyclic Redundancy Check Code (CRCC) generating/checking circuitry, as used in computer systems, is built without the need of a high speed shift clock. The circuit is built around latches and exclusive OR gates and so that the high speed Cyclic Redundancy Check (CRC) generating/checking operation is dependent only on the propagation delay of exclusive OR Tree circuitry. In prior art, CRC generating/checking circuitry encountered Electromagnetic Compatibility (EMC) problems because of the use of a shift clock. The technique described herein eliminates the need for a clock by generating an exclusive OR Tree in providing redundancy checking of serial bit streams.

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Cyclic Redundancy Check Code (Crcc) Generating/Checking Logic

A technique is described whereby high speed Cyclic Redundancy Check Code (CRCC) generating/checking circuitry, as used in computer systems, is built without the need of a high speed shift clock. The circuit is built around latches and exclusive OR gates and so that the high speed Cyclic Redundancy Check (CRC) generating/checking operation is dependent only on the propagation delay of exclusive OR Tree circuitry. In prior art, CRC generating/checking circuitry encountered Electromagnetic Compatibility (EMC) problems because of the use of a shift clock. The technique described herein eliminates the need for a clock by generating an exclusive OR Tree in providing redundancy checking of serial bit streams. The CRC equation for generating an exclusive OR is: G( x ) = x16 + x15 + x2 + 1 In the prior art, the circuit for generating a bit CRC would be as shown in Fig. 1, while the circuit for generating an exclusive OR Tree for byte CRC is shown in Fig. 2 Given the equation G (x) for either a 16- or a 32-bit CRC, an exclusive OR Tree can be generated, as shown in Fig. 3. Using an exclusive OR gate, the propagation delay is approximately 120 nanoseconds through the exclusive OR Tree. With this concept, the CRC generating/ checking operates at arate of 53.3 MHz, but does not require a 53.3 MHz shift clock, thereby eliminating EMC problems.

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