Browse Prior Art Database

Leakage and Noise Protection by Broadside Early Spill of Zero Cells

IP.com Disclosure Number: IPCOM000060844D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Lewellen, DK: AUTHOR [+3]

Abstract

In Shared Word Line (SWL) Random-Access Memory (RAM) arrays, cells written to "zero", e.g., at cell node 4, can leak, couple or be written to a lower than desired voltage. These cells could interfere with reading a "one" stored in a cell on the same bit line. To avoid these problems, this circuit utilizes the standby portion of the cycle to simultaneously cause any cells written to a weak level zero to spill charge and adjust them to a predetermined level. This level is selected to be sufficient to adequately isolate all the cells which were written in the zero state. The circuit shown provides charge sharing between word lines as follows: The unhook signal is brought low, which floats the couple node.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 78% of the total text.

Page 1 of 2

Leakage and Noise Protection by Broadside Early Spill of Zero Cells

In Shared Word Line (SWL) Random-Access Memory (RAM) arrays, cells written to "zero", e.g., at cell node 4, can leak, couple or be written to a lower than desired voltage. These cells could interfere with reading a "one" stored in a cell on the same bit line. To avoid these problems, this circuit utilizes the standby portion of the cycle to simultaneously cause any cells written to a weak level zero to spill charge and adjust them to a predetermined level. This level is selected to be sufficient to adequately isolate all the cells which were written in the zero state. The circuit shown provides charge sharing between word lines as follows: The unhook signal is brought low, which floats the couple node. Then phase pull-down (/PD) going high couples the unselected word line (WLU) and selected word line (WLS) to achieve a desired level (above ground) of all word lines as the SWL array is going into standby. Note, the magnitude of level a in Fig.2 is controlled by the ratio of the word line capacitance to gate-to-source capacitance of the devices connected to /PD. With the word line voltages down, the plate lines 2 that are not already at a low level are brought to a low level. When the plate line voltages are brought down, any zeros in the array will spill a quantity of charge which can be adjusted by the word line low level a (Fig. 2). Next, the plate lines rise and the word lines are brought to a...