Browse Prior Art Database

Dynamic RAM Refresh Controller

IP.com Disclosure Number: IPCOM000060849D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Cook, TE: AUTHOR

Abstract

A dynamic random-access memory (RAM) 1 requires a periodic refresh of its storage cells. Each RAM cell must be refreshed at least once per interval T (one millisecond). If there are N (128) refresh cycles needed to refresh all cells of the dynamic RAM, then the refresh access time must be at least once every t=T/N (8 microseconds). The overall concept is to perform a refresh operation at least once every eight microseconds; however, if the RAM is not being used, then perform a refresh during every address bus cycle time. The counter 2 is incremented every time a refresh operation occurs, and the value of the counter is used as the address for the next refresh of the RAM 1.

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Dynamic RAM Refresh Controller

A dynamic random-access memory (RAM) 1 requires a periodic refresh of its storage cells. Each RAM cell must be refreshed at least once per interval T (one millisecond). If there are N (128) refresh cycles needed to refresh all cells of the dynamic RAM, then the refresh access time must be at least once every t=T/N (8 microseconds). The overall concept is to perform a refresh operation at least once every eight microseconds; however, if the RAM is not being used, then perform a refresh during every address bus cycle time. The counter 2 is incremented every time a refresh operation occurs, and the value of the counter is used as the address for the next refresh of the RAM 1. The RAM 1 shares the same address bus as the register 3, the first-in, first-out (FIFO) queues 4 and the read-only memory (ROM) 5, and, therefore, during some address bus cycles, the RAM will not be accessed. This circumstance is detected by the decoder 6 which decodes whether the RAM is being used based upon the address on the address bus. If the address indicates that the RAM is being used, then an enabling signal is output on line 7 to the multiplexer 8, connecting the input address bus 9 to the address input of the dynamic RAM 1. An up/down counter 11 counts down four microsecond clock pulses and counts up for each refresh cycle. If 16 microseconds elapse without a refresh cycle, the counter 11 will output a signal on line 12 to the bus arbitrator 13 to use th...