Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Static Ram Cell Configuration

IP.com Disclosure Number: IPCOM000060861D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Chin, D: AUTHOR [+2]

Abstract

This article relates generally to solid-state memory cells and, more particularly, to a compact, static random-access memory cell. Increased packaging density of static random-access memory (SRAM) cells can be achieved by employing a silicon tunnel diode with two field-effect transistors (FETs) for the cell structure, similar to dynamic random-access memory (DRAM). Two examples of SRAM cells are schematically illustrated in Figs. 1A and 2A with their respective device structures shown in Figs. 1B and 2B. Each cell has an enhancement-type FET Q1, depletion-type FET Q2 and silicon tunnel diode (TD). A typical diagram of current versus voltage characteristics for a tunnel diode is shown in Fig. 3. In the circuit in Figs.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 74% of the total text.

Page 1 of 2

Static Ram Cell Configuration

This article relates generally to solid-state memory cells and, more particularly, to a compact, static random-access memory cell. Increased packaging density of static random-access memory (SRAM) cells can be achieved by employing a silicon tunnel diode with two field-effect transistors (FETs) for the cell structure, similar to dynamic random-access memory (DRAM). Two examples of SRAM cells are schematically illustrated in Figs. 1A and 2A with their respective device structures shown in Figs. 1B and 2B. Each cell has an enhancement-type FET Q1, depletion-type FET Q2 and silicon tunnel diode (TD). A typical diagram of current versus voltage characteristics for a tunnel diode is shown in Fig. 3. In the circuit in Figs. 1A and 1B, when Q1 turns on with VDD applied to both word and bit lines, additional current flows through diode TD, forcing it to the temporary position "1t" in Fig. 3. When cell selection is reset, the current through diode TD is reduced so it drops back to stable position "1" in Fig. 3. Grounding the bit line and selecting the word line with VDD diverts current from diode TD, forcing it first to the '0t' position, then returning to the '0' position after the bit line selection signal is removed. The state of the tunnel diode is static, being changed only by input signals, so that memory refresh is not required. Stored data is read through the bit line as in a DRAM. In the circuit of Figs. 2A and 2B, Q1 is on when the...