Browse Prior Art Database

Enable/Disable and Card ID Port for Memory Card

IP.com Disclosure Number: IPCOM000060873D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 115K

Publishing Venue

IBM

Related People

Itoh, H: AUTHOR

Abstract

This article describes an input/output (I/O) port control for plural memory cards which are optionally mounted on a system bus. Each memory card is provided with a card identification (ID) circuit and an enable/disable flip-flop (FF) circuit. All card IDs of the memory cards are simultaneously read by one I/O Read instruction with a particular I/O address. Similarly all enable/disable FF circuits of the memory cards are also set or reset in parallel by one I/O Write instruction with this particular address. The figure shows a block diagram of one memory card including a 1 megabyte (MB) random-access memory (RAM) 10, a dual inline package (DIP) switch 11, a card ID circuit 12, an address match circuit 13, an enable/disable circuit 14 and a data buffer 15. The DIP switch 11 comprises four switches, i.e.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 2

Enable/Disable and Card ID Port for Memory Card

This article describes an input/output (I/O) port control for plural memory cards which are optionally mounted on a system bus. Each memory card is provided with a card identification (ID) circuit and an enable/disable flip-flop (FF) circuit. All card IDs of the memory cards are simultaneously read by one I/O Read instruction with a particular I/O address. Similarly all enable/disable FF circuits of the memory cards are also set or reset in parallel by one I/O Write instruction with this particular address. The figure shows a block diagram of one memory card including a 1 megabyte (MB) random-access memory (RAM) 10, a dual inline package (DIP) switch 11, a card ID circuit 12, an address match circuit 13, an enable/disable circuit 14 and a data buffer 15. The DIP switch 11 comprises four switches, i.e., SW1, SW2, SW3 and SW4, which are used to set the card start address. The following table shows the switch settings and the I/O address assignments for fifteen 1 MB memory cards.

(Image Omitted)

For card ID read and enable/disable control operations, Address X'abcd' is commonly used, and fifteen data bits D1, D2, ... D15 on a data bus are assigned to the fifteen memory cards, respectively. As for the card ID read operation, the card ID circuit 12 associated with the DIP switch 11 is responsive to I/O Read and Address X'abcd' signals from a microprocessor (not shown) to set one of the data bits D1 - D15 to "0" and the o...