Browse Prior Art Database

OVERLAY LINKER and LOADER Process

IP.com Disclosure Number: IPCOM000060897D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 49K

Publishing Venue

IBM

Related People

Hoegh, BT: AUTHOR [+4]

Abstract

Traditionally, a linker is used to combine a set of subprograms together to form a composite program which is usually called load module, and a loader is responsible to load the load module into memory. Moreover, the loader has to map the module's logical address space into a physical one. This transition is sometimes referred to as address binding. Often, the linking and loading process is static and initiated by a user, and ends here. In this arrangement, the process is taken another step further by linking a set of independently compiled and linked modules together to form an executable system and overlaying it into two different physical memory spaces - one on the Personal Computer (PC) random-access memory (RAM), and the other on a Communication Card (CC).

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OVERLAY LINKER and LOADER Process

Traditionally, a linker is used to combine a set of subprograms together to form a composite program which is usually called load module, and a loader is responsible to load the load module into memory. Moreover, the loader has to map the module's logical address space into a physical one. This transition is sometimes referred to as address binding. Often, the linking and loading process is static and initiated by a user, and ends here. In this arrangement, the process is taken another step further by linking a set of independently compiled and linked modules together to form an executable system and overlaying it into two different physical memory spaces - one on the Personal Computer (PC) random- access memory (RAM), and the other on a Communication Card (CC). However, this process is dynamic and initiated by an application program on the fly. In order to support a general purpose CC, code overlaying and down-loading is necessary. The overlay linkage and loader will now be described. THE LINKER The linker must combine a set of object modules into an executable system, as illustrated in Fig. 1. Therefore, the main function of the linker is linking together PC and CC and Signal Processing (SP) code. The inputs to the linker can be divided into three groups: the linkage table, the PC modules, and the SP modules. 1. The Linkage Table The linkage table contains entries pointing to linked modules. The first entry in the table contains the path name which defines the searching path for the modules.

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The remaining entries in the table have the following simplified format:

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where each field is defined as below: FSID -- Function Set Identification Version -- Version Number PC Name -- PC load module name Size -- Size of load module SP Name -- SP load module name At link time, the linker updates the path name in the first entry of the linkage table, the PC and SP names, and the sizes of the load modules. 2. The PC Module The PC module is pointed to by a pointer in the linkage table. The module has three main parts: the header, code for regular routines, and code for interrupt handlers, as illustrated in Fig. 2.
a. The header The header is composed of pointers to the regular routines. The first entry points to a list of command pointers which point to routines in the regular codes. The second entry points to a list of interrupt pointers which point to interrupt handlers. 3. The SP Module The SP module contains more information. It mainly has four parts: a header, TMS codes, Data, and the END Mark, as shown in Fig. 3 a. The SP header The SP header contains four important pointers. The code pointer points to the last subheader in the SP microcode portion. The subheader will be described later in more detail. Likewise, the Control Block (CB) pointer, and the Internal Data Memory (IDM) pointer point to the last subheader in each of the data portions. Finally, the END pointer points...