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Implementing Bipolar Transistors and Capacitors in CMOS Circuits

IP.com Disclosure Number: IPCOM000060899D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Ames, RD: AUTHOR [+3]

Abstract

Current CMOS technologies offer only N and P channel transistors in their device set. A cross-section of these two devices is illustrated in Fig. 1. Here, the P-channel transistor is formed with a P implant 2 in the N type well 1. The N-channel transistor is formed with an N implant 3 in the bulk P epitaxial material. Additional devices can be formed by the inclusion of two extra implants in the processing sequence. One of the devices formed is a bipolar NPN transistor (Fig. 2). Here, the existing N well structure 1 forms the collector of the device. The base 4 is formed with an additional P type implant. The emitter of the device is formed by using the existing implant that forms the N channel source and drain 3. Another device that proves desirable is a gate-oxide capacitor. This device, also shown in Fig.

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Implementing Bipolar Transistors and Capacitors in CMOS Circuits

Current CMOS technologies offer only N and P channel transistors in their device set. A cross-section of these two devices is illustrated in Fig. 1. Here, the P-channel transistor is formed with a P implant 2 in the N type well 1. The N- channel transistor is formed with an N implant 3 in the bulk P epitaxial material. Additional devices can be formed by the inclusion of two extra implants in the processing sequence. One of the devices formed is a bipolar NPN transistor (Fig. 2). Here, the existing N well structure 1 forms the collector of the device. The base 4 is formed with an additional P type implant. The emitter of the device is formed by using the existing implant that forms the N channel source and drain
3. Another device that proves desirable is a gate-oxide capacitor. This device, also shown in Fig. 2, is constructed by adding an N implant 5 before the gate- oxide 6 is grown. During the process sequence, the two additional implants must be added such that the existing N and P channel device set is not affected. The two extra implants need to be done after the isolation oxide growth 7 (Figs. 1 and
2). The location in the process sequence that best satisfies this requirement is immediately after the removal of the pad nitride. Fig. 3 shows the vertical cross- section immediately prior to the removal of the nitride. The silicon nitride 8 and silicon dioxide 9 sandwich prevent the thick oxide...