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Fast Read-Out of Twin Four-Square Array by "Local Potential Equilibration"

IP.com Disclosure Number: IPCOM000060916D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 74K

Publishing Venue

IBM

Related People

Brigida, DJ: AUTHOR [+2]

Abstract

A choice of new operating conditions is described for a twin 4-square memory cell [*] which results in immediate localized equilibration of the stored charge. This mode of operation has the advantage of improved performance, with the position of the cell not being relevant to performance. As shown in Fig. 1, which is a sectional view taken through a word line 10 of a twin 4-square memory cell, a first storage capacitor 11 which includes a bit/sense line left BSL and a first N diffusion region 1 having a thin dielectric layer 3 interposed therebetween and a second storage capacitor 12 which includes a second bit/sense line right BSR and a second N diffusion region 2 also having layer 3 interposed therebetween. Regions 1 and 2 are disposed at the surface of semiconductor substrate 20 made of P type material.

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Fast Read-Out of Twin Four-Square Array by "Local Potential Equilibration"

A choice of new operating conditions is described for a twin 4-square memory cell [*] which results in immediate localized equilibration of the stored charge. This mode of operation has the advantage of improved performance, with the position of the cell not being relevant to performance. As shown in Fig. 1, which is a sectional view taken through a word line 10 of a twin 4-square memory cell, a first storage capacitor 11 which includes a bit/sense line left BSL and a first N diffusion region 1 having a thin dielectric layer 3 interposed therebetween and a second storage capacitor 12 which includes a second bit/sense line right BSR and a second N diffusion region 2 also having layer 3 interposed therebetween. Regions 1 and 2 are disposed at the surface of semiconductor substrate 20 made of P type material. A word line charge transfer device 13 including segment 14 of word line 10 and channel region 15 located at the surface of substrate 20 is disposed between the first and second storage capacitors 11 and 12. The twin cell storage capacitors 11 and 12 have complementary charges stored, resulting in a pair of high "0" and low "1" storage potentials. A plurality of other similar twin cells (not shown) are disposed along word line 10. Channel region 15 and other similar channel regions (not shown) disposed along word line 10 are fabricated so as to provide a threshold voltage of substantially zero volts. In the operation of the twin cell, it is assumed initially that the bit/sense lines BSL and BSR are precharged to 5 volts, and the word line is grounded. The surface potential under the bit/sense line corresponds to the charge stored for a complementary pair, i.
e., "0" and "1". The N+ diffusion region connected to a +5 volt potential source provides the initial information charge "0" and "1" complementary pattern when the chip is first powered on. Schematically, the twin cell shown in Fig. 1 has a surface potential profile "A" for the store "one" state. To execute a READ operation, the selected word line 10 is pulsed on (0 to 8.5 volts), as indicated in Fig. 2. The surface potential...