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Byte-Wide Implementation of RLL (1,7) Code

IP.com Disclosure Number: IPCOM000060920D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Greenberg, R: AUTHOR [+2]

Abstract

The run-length-limited (RLL) (1,7) encoding algorithm, as defined, generates three encoded bits for each two data bits. The implementation shown herein allows simultaneous encoding of an entire byte. This has such advantages as permitting a portion of the logic to operate at 1/4 speed; requiring register REG1 to parallel load only and not shift; and enabling two of the state latches to be made to be equal to two bits from the preceding data byte which eliminates the next state logic for these latches. This last feature is also attractive if a wrap check is included, since the latches may already exist in the design. Twelve encoded bits are generated at a time and consequently register REG2 must contain 12 latches.

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Byte-Wide Implementation of RLL (1,7) Code

The run-length-limited (RLL) (1,7) encoding algorithm, as defined, generates three encoded bits for each two data bits. The implementation shown herein allows simultaneous encoding of an entire byte. This has such advantages as permitting a portion of the logic to operate at 1/4 speed; requiring register REG1 to parallel load only and not shift; and enabling two of the state latches to be made to be equal to two bits from the preceding data byte which eliminates the next state logic for these latches. This last feature is also attractive if a wrap check is included, since the latches may already exist in the design. Twelve encoded bits are generated at a time and consequently register REG2 must contain 12 latches. In practice, many or all of these latches will already be present due to the requirements of decoding and sync byte detection. The block diagram is shown in Fig. 1. To generate the logic, states XS-2S-1 = 000, 001, 010, 011, 110, and 111 are used. The values of S1 and S0 are chosen with S0 designated as the high-order bit. Then, the next state of S-2 is S0 and of S-1 is S1 . The state sequence table is shown in Table 1. The equations are: Y'2 = S-2 X- X' = S-1S0X- Y'1 = S- -2(S- -1+S0S1) S-2 = S0 Y'0 = S-1S- 0S- 1X- S-1 = S1 By making subscript changes in these equations, we can write the Ys and Xs for an entire byte of customer data. Customer byte - S0S1S2S3S4S5S6S7 Encoded data = Y'2 Y'1 Y'0 Y''2 Y''1 Y''0 Y'...