Browse Prior Art Database

Multiple Frequency Data Clock Using Phase-Locked Loop

IP.com Disclosure Number: IPCOM000060924D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Gillingham, RD: AUTHOR

Abstract

This article describes a circuit for synchronizing a logic clock signal to one of several possible data frequencies when reading data from external media. The figure is a block diagram of the circuit to be described. A phase-locked loop locks the phase of an output clock, STDCLK, to read data signals, RDATA, typically from a diskette unit. The circuit includes features to operate with several units having different data rates. Charge-pumped, phase-locked oscillators with bandwidth controlled charge pump and loop filters including output dividers are described in the prior art [1]. Selecting different data rates involves changing the frequency of a VCO 14 and the period of a one-shot multivibrator 20. The function of the one-shot (20) can be performed by other types of circuits, e.g., delay circuits.

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Multiple Frequency Data Clock Using Phase-Locked Loop

This article describes a circuit for synchronizing a logic clock signal to one of several possible data frequencies when reading data from external media. The figure is a block diagram of the circuit to be described. A phase-locked loop locks the phase of an output clock, STDCLK, to read data signals, RDATA, typically from a diskette unit. The circuit includes features to operate with several units having different data rates. Charge-pumped, phase-locked oscillators with bandwidth controlled charge pump and loop filters including output dividers are described in the prior art [1]. Selecting different data rates involves changing the frequency of a VCO 14 and the period of a one-shot multivibrator 20. The function of the one-shot (20) can be performed by other types of circuits, e.g., delay circuits. The VCO frequency is divided by integer steps using digital frequency dividers 15. Division by 2, 4, and 8 is illustrated, but other integer divisors are possible. Noninteger changes in the VCO frequency can be made by varying the analog bias in the VCO if the latter is typically an emitter-coupled oscillator having a frequency directly related to the bias current. Increasing the reference bias current from the generator 21 increases the VCO frequency. The period of the one-shot 20 must be adjusted in the same manner, integer and noninteger steps, as the VCO. In the illustrated circuit, the one-shot integer step variations are obtained by changing the one- shot biasing current supplied from...