Browse Prior Art Database

Architecture for Reconfigurable Processing Subsystem

IP.com Disclosure Number: IPCOM000060929D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Flickner, MD: AUTHOR [+4]

Abstract

Disclosed is a processing architecture that supports parallel, pipelined modules that can be easily reconfigured for different applications. The architecture includes a plurality of functional modules interconnected through multiple busses and a controller isolating the multiple modules from the host bus that sets up various registers in the different modules and monitors the progress of operations occurring in the system. The figure illustrates the basic structure of the disclosed architecture. The functional modules 10 provide processing support for steps required in a given system, such as an image inspection system. For example, an arithmetic processor 11 may do grading operations, a logic processor 12 may do thresholding, a component labeling and feature memory module 13 may do feature extraction, and so on.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Architecture for Reconfigurable Processing Subsystem

Disclosed is a processing architecture that supports parallel, pipelined modules that can be easily reconfigured for different applications. The architecture includes a plurality of functional modules interconnected through multiple busses and a controller isolating the multiple modules from the host bus that sets up various registers in the different modules and monitors the progress of operations occurring in the system. The figure illustrates the basic structure of the disclosed architecture. The functional modules 10 provide processing support for steps required in a given system, such as an image inspection system. For example, an arithmetic processor 11 may do grading operations, a logic processor 12 may do thresholding, a component labeling and feature memory module 13 may do feature extraction, and so on. Additional modules 10 may be added for different applications. The architecture supports multiple modules of a certain function to support parallel operations, as, for example, in horizontal and vertical boundary fitting in image processing. The modules are connected together in an arbitrary order across a flexible bus structure 15 which includes multiple data busses. The multiple busses provide for increased bandwidth and support parallel pipelined operations. Preferably, the busses are time multiplexed to provide more logical busses (phase 1, phase 2) than are physically available. The bus structure 15 supports modules of different speeds cascaded together within a synchronous framework by providing a communication protocol that includes two tag bits per bus to indicate whether a certain item being transferred was valid or not. Though one bit is sufficient for this purpose, an add...