Browse Prior Art Database

Video Interface Circuit

IP.com Disclosure Number: IPCOM000060934D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Persh, RB: AUTHOR

Abstract

The figure illustrates a circuit which enables a microcomputer having limited speed and memory to convert high speed video signals into digital data signals. A video receiver 10 transmits an input signal generated by a camera to a sync circuit 12 and to a correction circuit 14. The sync circuit 12 generates a vertical sync signal and a horizontal sync signal. The correction circuit 14 utilizes the horizontal sync signal to generate a five-volt, ground-referenced video signal. The video signal is then transmitted to a sample and hold circuit 16 for storage therein. The vertical sync signal is logically combined with a master clock signal to produce a clock signal which enables a counter/latch circuit 18 to divide the video signal into a plurality of equal segments.

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Video Interface Circuit

The figure illustrates a circuit which enables a microcomputer having limited speed and memory to convert high speed video signals into digital data signals.

A video receiver 10 transmits an input signal generated by a camera to a sync circuit 12 and to a correction circuit 14. The sync circuit 12 generates a vertical sync signal and a horizontal sync signal. The correction circuit 14 utilizes the horizontal sync signal to generate a five-volt, ground-referenced video signal. The video signal is then transmitted to a sample and hold circuit 16 for storage therein. The vertical sync signal is logically combined with a master clock signal to produce a clock signal which enables a counter/latch circuit 18 to divide the video signal into a plurality of equal segments. The counter/latch circuit 18, after a predetermined count, generates a start-convert pulse which enables an analog- to-digital converter 20 to convert the video signal stored in the sample and hold circuit 16 and quantize it into eight digital bits. Moreover, as the video signal is divided into segments, an address is assigned to each of the segments thereof which allows the analog-to-digital converter 20 to convert one segment per vertical sync signal. Thereafter, the address is incremented and the conversion process continues. The quantized video signal is then fed to a computer data bus 22. The counter/latch circuit 18 also receives data signals from the computer data bus 22 w...