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Line Quiesce Pattern-Correction Circuit

IP.com Disclosure Number: IPCOM000060935D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Carissimo, DJ: AUTHOR [+3]

Abstract

National Semiconductor's DP8340 Serial Bi-phase Transmitter/Encoder chips cause intermittent transmit checks on some devices. The correct DCA (Device Cluster Adapter) waveform (Fig. 1) pattern has a series of five 1's which form a line quiesce pattern and then a mini-code violation signals the start of valid data. Some DCA receiver devices look for a mini-code violation and a number of preceding 1's of the line quiesce pattern to signal the start of valid data. This is the correct interpretation. However, other devices only look for the mini-code violation.

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Line Quiesce Pattern-Correction Circuit

National Semiconductor's DP8340 Serial Bi-phase Transmitter/Encoder chips cause intermittent transmit checks on some devices. The correct DCA (Device Cluster Adapter) waveform (Fig. 1) pattern has a series of five 1's which form a line quiesce pattern and then a mini-code violation signals the start of valid data. Some DCA receiver devices look for a mini-code violation and a number of preceding 1's of the line quiesce pattern to signal the start of valid data. This is the correct interpretation. However, other devices only look for the mini-code violation. If a device has an incorrect waveform, start on the line quiesce pattern before a coax cable has established an equilibrium switching condition, and is intermittently interpreted by the receiver as a mini-code violation, it will result in transmit checks on those devices that are only looking for a mini-code violation to signal the start of valid data. This malfunction is corrected by the circuitry described below. A 4-bit shift register 1 (Fig. 2) delays the start of the transmitter active delayed line 2 which enables the coax cable driver 3. This eliminates the irregular waveform seen in the timing diagram (Fig. 1). The shift register 1 is cleared by the transmitter active line 4 going inactive (logic 0), thus delaying the start of the transmitter active signal. The corrected waveform (Fig. 1) provides for reliable operation of the DP8340 on all DCA devices.

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