Browse Prior Art Database

Variable Start Location Circuitry for a Display Ram Secondary Port Shift Register

IP.com Disclosure Number: IPCOM000060940D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Gray, KS: AUTHOR

Abstract

An enhancement for a two-port Display-RAM (D-RAM) is described in which each stage of the parallel-loaded secondary port shift register is made independently accessible. Each of the shift register stages (S.R.S.) are capable of being independently coupled to a common data input/output bus in response to a plurality of decoders, in turn, responsive to a serial data start address. Circuitry that allows any bit in a D-Ram secondary port shift register string to be the first bit for both reading and writing is shown in the figure. With the circuitry (within the dashed line enclosure) repeated between register (S.R.S.) pairs at each potential starting point, all bits can be rippled through. Steering transistors T1, T4, and T5 and a register bit decoder (RBD) 2 are required for each possible starting position.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Variable Start Location Circuitry for a Display Ram Secondary Port Shift Register

An enhancement for a two-port Display-RAM (D-RAM) is described in which each stage of the parallel-loaded secondary port shift register is made independently accessible. Each of the shift register stages (S.R.S.) are capable of being independently coupled to a common data input/output bus in response to a plurality of decoders, in turn, responsive to a serial data start address. Circuitry that allows any bit in a D-Ram secondary port shift register string to be the first bit for both reading and writing is shown in the figure. With the circuitry (within the dashed line enclosure) repeated between register (S.R.S.) pairs at each potential starting point, all bits can be rippled through. Steering transistors T1, T4, and T5 and a register bit decoder (RBD) 2 are required for each possible starting position. The RBD uses address T/C (true/complement) inputs 4 to generate a 1 of N decode pulse at node A. One node A will be up, and all the others will be down. The RBD output is then generated each time the parallel data from the memory is loaded into the shift register string, and has to stay valid through the entire shifting out and/or shifting in sequence. Any one of a number of available decoders can be used for this purpose. For all starting positions except for one, node A is down. Transistors T4 and T5 are off, and transistor T1 is on because of the inverter action of transistors T2 and T3. Thus, for all positions except one, one shift registe...