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Measurement of Small Junction Capacitances

IP.com Disclosure Number: IPCOM000060943D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Malaviya, SD: AUTHOR

Abstract

In the manufacture of semiconductors, capacitance measurements may be used to develop models or control a manufacturing process. There is a problem with the measurement of small or low capacitance structures where the probe and pad of ordinary means is large enough to interfere with the accuracy of the measurement. An invention proposes a circuit design integrated on the same chip so that the differential channels, which are a form of a capacitance measurement circuit, are balanced within the limits of on-chip tracking. The proposed technique is based on probing the device under test with a signal which is small in amplitude, e.g., 1 millivolt, but high in frequency, e.g., 100 MHz.

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Measurement of Small Junction Capacitances

In the manufacture of semiconductors, capacitance measurements may be used to develop models or control a manufacturing process. There is a problem with the measurement of small or low capacitance structures where the probe and pad of ordinary means is large enough to interfere with the accuracy of the measurement. An invention proposes a circuit design integrated on the same chip so that the differential channels, which are a form of a capacitance measurement circuit, are balanced within the limits of on-chip tracking. The proposed technique is based on probing the device under test with a signal which is small in amplitude, e.g., 1 millivolt, but high in frequency, e.g., 100 MHz. The probing signal is amplified to about 10 millivolts by a built-in amplifier and its frequency is then brought down sharply to 1-10 KHz before being brought out to a pad for measurement by external meters. The circuitry insures that there is no change in the amplitude of the signal during frequency reduction and the problems associated with the measurement of high frequency signals are eliminated. The circuit consists of ordinary practical elements with a block schematic shown in Fig. 1. High frequency current J1 is fed to the input pad P1 of a current splitter. One half of the output current is fed to a standard reference 1K ohm resistor R' with the other half fed to the device under test represented by its equivalent resistance R and shunt capacitance C. Voltages developed across R' and R are fed to the high frequency DC coupled amplifiers 1 and 2, respectively. The amplifiers are designed to accommodate changes in the input DC levels, although this requirement limits their gain to N10. The outputs of the amplifiers are fed to buffers 1 and 2 to isolate them from the mixer where another high frequency signal E1 is mixed with the amplified signals to produce beat frequency outputs at a low frequency in the 1-10 KHz range. The second signal E1 is made sufficiently large N0.5 to 1 volt to linearize the outputs of the diode detectors used in the demodulators 1 and 2. This arrangement provides that the magnitudes of the low frequency output signals are exactly equal to the magnitudes of the high frequency outputs from the buffers. Measurement of the ratio of the low frequency output signals from the demodulators will give the ratio of the voltages developed across R and R' at 100 MHz. This circuitry also permits direct measurement of the values of R and R'. Both R and C can b...