Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Random-Access Memory Sequence Simulator/Emulator for Hierarchical Multilevel Arrays

IP.com Disclosure Number: IPCOM000060956D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 80K

Publishing Venue

IBM

Related People

Graybill, JH: AUTHOR [+5]

Abstract

A technique is described to achieve hardware In-Circuit-Emulation of hierarchical multilevel control systems. The In-Circuit-Emulation is accomplished by a random-access memory (RAM)-based hardware emulator. This hardware emulator is supported by a software package development tool and a download sequencer development tool. A typical RAM array, as shown in Fig. 1, may be used to emulate the AND/OR array of a PLA. It is programmable and reprogrammable, thus eliminating the need to program the PLA during the development of hardware. The higher-order 4-bits of address bus 10 represents the present state function so that the configuration can support and define an algorithm state machine (ASM) with sixteen states. In any of the sixteen possible states, the machine may sample 256 different combinations of eight inputs.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

Random-Access Memory Sequence Simulator/Emulator for Hierarchical Multilevel Arrays

A technique is described to achieve hardware In-Circuit-Emulation of hierarchical multilevel control systems. The In-Circuit-Emulation is accomplished by a random-access memory (RAM)-based hardware emulator. This hardware emulator is supported by a software package development tool and a download sequencer development tool. A typical RAM array, as shown in Fig. 1, may be used to emulate the AND/OR array of a PLA. It is programmable and reprogrammable, thus eliminating the need to program the PLA during the development of hardware. The higher-order 4-bits of address bus 10 represents the present state function so that the configuration can support and define an algorithm state machine (ASM) with sixteen states. In any of the sixteen possible states, the machine may sample 256 different combinations of eight inputs. The higher-order 4-bits of the data output 11 generates the next state function to the D-register 12, while the lower- order 4-bits 13 are the conditional and unconditional outputs. Since up to 256 combinations of the eight inputs may not be needed, it is possible to optimize the sequencer, as shown in Fig. 2, to provide a sampling of three inputs in each state. By using three 8 to 1 multiplexers 14, the RAM size is compressed address-wise and expanded data- wise. Since the address compression is exponential and the data expansion is linear, the RAM size is greatly reduced. A system requiring sixteen states and eight inputs sampled three at a time requires a 128 x 17 RAM 15. Nine data bits are required, three octal digits, to specify the inputs of each state. To support thirty-two states, a 256-bit RAM would be required. Thus, it can be seen that instead of requiring 32,768 bits, as in the 4K x 8-bit array in Fig. 1, the compressed RAM requires only 2,176 bits in the 128 x 17-bit array in Fig. 2. Since the RAM size has been reduced, the amount of hardware and software needed to load the RAM has also been reduced. The hardware emulator development tool utilizes a series of RAMs 16, as shown in Fig. 3, to simulate proper machine speeds. The hardware surrounding the RAMs must have tri- state outputs to enable programming and system operation with continuous power supplied to the RAMs. When in run mode, the address drivers 18 and address receivers 17 are active. In program mode they are inactive. The download sequencer controls the hardware emulator tool to program RAM-based sequencer that simulate...