Browse Prior Art Database

Dynamic Logic Array

IP.com Disclosure Number: IPCOM000060959D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Bonetti, B: AUTHOR [+2]

Abstract

The circuit is a software alterable programmable logic array (PLA) with additional alterable input and output functions. Personalization is achieved (see part (A) of the drawing) through the provision of a shift register latch (SRL) 10 and a logic switch (LS) 12 at each node of the AND array 2, OR array 4, and any other programmable nodes, such as the programmable input function (PIF) 6 or programmable output functions (POF) 8 of the PLA. The SRL 10/LS 12 combination is analogous to the fusible link in a standard fusible programmable logic array. The SRL 10 controls the LS 12. The SRLs 10 are connected in one serial scan path throughout the entire module. In the AND array 2, a "1" programmed into the SRL 10 causes LS 12 to transfer the output of decoder 14 to product term node 16.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 56% of the total text.

Page 1 of 2

Dynamic Logic Array

The circuit is a software alterable programmable logic array (PLA) with additional alterable input and output functions. Personalization is achieved (see part (A) of the drawing) through the provision of a shift register latch (SRL) 10 and a logic switch (LS) 12 at each node of the AND array 2, OR array 4, and any other programmable nodes, such as the programmable input function (PIF) 6 or programmable output functions (POF) 8 of the PLA. The SRL 10/LS 12 combination is analogous to the fusible link in a standard fusible programmable logic array. The SRL 10 controls the LS 12. The SRLs 10 are connected in one serial scan path throughout the entire module. In the AND array 2, a "1" programmed into the SRL 10 causes LS 12 to transfer the output of decoder 14 to product term node 16. A "0" programmed into SRL 10 will cause the LS 12 to set that node to a "don't care" state. Similarly, in the OR array 4, the SRL 10/LS 12 combination determines whether the respective PT 16 will be connected to the OR term (OT) 18. The circuit contains additional input and output functions. The input functions include a decoder 14 which is always active. The decoder decodes a pair of inputs to generate four unique functions at the AND array 2 nodes. By programming the AND array 2 nodes SRL 10, and thus connecting various combinations of the four output functions of decoder 14 to PT 16, up to 16 unique logical functions such as input A AND input B, input A OR input B...