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High Speed Parallel SIGNATURE Board

IP.com Disclosure Number: IPCOM000060963D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 4 page(s) / 61K

Publishing Venue

IBM

Related People

Chui, WK: AUTHOR

Abstract

A circuit board is disclosed which is capable of converting eight different digital data streams into eight independent 16-bit signatures simultaneously. The signature generators used are of the high-speed "look-ahead" type, using only two temporary storage elements as compared to three required in the conventional design. Fig. 1 shows one of the eight identical circuits used in the board. The circuits consist of three major functional parts as follows: 1) DATA INPUT CONDITIONING CIRCUITS consist of Q1, D1, R1, R2, R3, R4, U1, and U2. The emitter follower comprising Q1, R2, R3, and R4 serves three purposes. A) To provide a high input impedance for the data input. B) To drop the data input voltage by approximately .65 volt (base-to-emitter voltage drop of Q1) before it feeds the inputs of comparators U1 and U2.

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High Speed Parallel SIGNATURE Board

A circuit board is disclosed which is capable of converting eight different digital data streams into eight independent 16-bit signatures simultaneously. The signature generators used are of the high-speed "look-ahead" type, using only two temporary storage elements as compared to three required in the conventional design. Fig. 1 shows one of the eight identical circuits used in the board. The circuits consist of three major functional parts as follows: 1) DATA INPUT CONDITIONING CIRCUITS consist of Q1, D1, R1, R2, R3, R4, U1, and U2. The emitter follower comprising Q1, R2, R3, and R4 serves three purposes.
A) To provide a high input impedance for the data input. B) To drop the data input voltage by approximately .65 volt (base-to-emitter voltage drop of Q1) before it feeds the inputs of comparators U1 and U2. This voltage drop allows the full TTL (transistor-transistor logic) input voltage range to be applied at DATA IN without exceeding the common voltage range of U1 and U2. C) To provide a well-defined input voltage when DATA IN is disconnected or floated as in the output of a tri-state device. R2, R3, and R4 bias the transistor Q1 in such a way that the voltage at the base of Q1 is in the range of 1.20 to 1.6 volts, when DATA IN is floated. This can be achieved by using a transistor with beta in the range of 350 to 500. R1 and D1 protect transistor Q1 when the input exceeds the +5 and - 5 volt range. Comparators U1 and U2 compare the emitter follower output with the reference voltages, HI-REF and LOW-REF, and generate digital voltages to feed the J-K Flip-Flop U3. For TTL signal, HI-REF is set at 1.35 volts which is 2 volts minus the base-to-emitter voltage drop of Q1. Similarly, LOW-REF is set at
0.15 volt to compensate for the base- to-emitter voltage drop. 2) DATA SAMPLER U3 The output of U3 at the active transition of CLK-A depends on the J and K inputs, as shown in the following table.

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It has been assumed that the voltage drop across R1 is negligible as is the case if Q1 is a transistor with its Beta in excess of 300. 3) SIGNATURE GENERATOR The signature generator comprising U4 through U11 is of the high speed "look-ahead" type. U5 is a 15-bit shift register which contains the most significant 15 bits of the signature at the end of a measurement period. U11 combines the output of D Flip-Flop U4 with bit 7 of U5 and forms the least significant bit of the signature. The novel feature of this high speed signature generator is the requirement of only two temporary storage elements U6 and U7 instead of three, as required in the conventional "look-ahead" high speed signature generator. It is the unique location of the XOR gate U11, which is inserted between the first two stages of the 16-bit shift register, that allows the elimination of an additional temporary storage element. CLK-B is similar to CLK- A, but is delayed by an amount at least equal to the sum of the propagation...