Browse Prior Art Database

Hiding of Store Protection Checks in a Pipelined System

IP.com Disclosure Number: IPCOM000060971D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Buterbaugh, EW: AUTHOR [+5]

Abstract

In a pipelined system, store protection checks prior to a store operation often add an extra cycle to the store time. During this extra cycle, checks are made on the addressed location to determine if a write to that location is a valid operation. The checks usually involve the reading of a memory location (either the location to receive the store data or a location in an auxiliary memory), and therefore cannot be performed in the same cycle as the store operation without increasing the cycle time. If the store protection check is executed in Cycle 5, seen in Fig. 1, immediately prior to the store cycle, Cycle 6, it adds an extra cycle to the store execution time. It is possible to hide this additional cycle in pipelined central processing unit (CPU) systems having operand prefetch.

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Hiding of Store Protection Checks in a Pipelined System

In a pipelined system, store protection checks prior to a store operation often add an extra cycle to the store time. During this extra cycle, checks are made on the addressed location to determine if a write to that location is a valid operation. The checks usually involve the reading of a memory location (either the location to receive the store data or a location in an auxiliary memory), and therefore cannot be performed in the same cycle as the store operation without increasing the cycle time. If the store protection check is executed in Cycle 5, seen in Fig. 1, immediately prior to the store cycle, Cycle 6, it adds an extra cycle to the store execution time. It is possible to hide this additional cycle in pipelined central processing unit (CPU) systems having operand prefetch. The better alternative is to perform the store protection check in its natural slot in the operand prefetch sequence, Cycle 3 (Fig. 1). This is the slot where an operand would have been fetched if the operation had been a read of memory rather than write. Fig. 2 shows the timing involved. As shown in Fig. 1, Cycle 3, the memory slot for Cycle 3 is normally not used. This method makes use of the wasted cycle to perform the store protection checks; thus, they are hidden and do not add an additional cycle to the store operation. This method applies whether protection information is stored in either the main memory or a dedicated sto...