Browse Prior Art Database

Polysilicon Fuse Structure

IP.com Disclosure Number: IPCOM000060972D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Scheuerlein, RE: AUTHOR

Abstract

A method is described for forming and contacting fuses comprised of polycrystalline silicon (polysilicon) in a CMOS process which is compatible with isotropic deposition of first metal, e.g., chemical vapor deposition (CVD) of tungsten, and anisotropic etching, e.g., reactive ion etching (RIE), of first metal. The method includes creating the fuse structure over an isolated N-well to avoid fuse-to-substrate short circuits. The cross-sectional view in Fig. 2, which is taken through line A-A of the plan view in Fig. 1, shows the N-well 2 formed in P- epitaxial silicon 4 which is deposited on P+ substrate 6. A deposited layer of silicon dioxide 8 is formed over this structure. A polysilicon layer 10 is deposited and etched to form the shape shown in the plan view of Fig. 1.

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Polysilicon Fuse Structure

A method is described for forming and contacting fuses comprised of polycrystalline silicon (polysilicon) in a CMOS process which is compatible with isotropic deposition of first metal, e.g., chemical vapor deposition (CVD) of tungsten, and anisotropic etching, e.g., reactive ion etching (RIE), of first metal. The method includes creating the fuse structure over an isolated N-well to avoid fuse-to-substrate short circuits. The cross-sectional view in Fig. 2, which is taken through line A-A of the plan view in Fig. 1, shows the N-well 2 formed in P- epitaxial silicon 4 which is deposited on P+ substrate 6. A deposited layer of silicon dioxide 8 is formed over this structure. A polysilicon layer 10 is deposited and etched to form the shape shown in the plan view of Fig. 1. In this CMOS process, a thin tungsten layer is next deposited over the entire surface and heat treated to cause formation of a tungsten silicide layer 12, wherever the tungsten contacts silicon. Pure tungsten is then removed by a selective etch process. A boron-phosphorous-silicon glass (BPSG) layer 14 is then deposited and an opening 15 in the BPSG 14 is etched by RIE producing near vertical sidewalls on the opening 15 in the BPSG 14. The CVD tungsten 16 is then deposited, photo processed for the first line and contact pattern, and RIE etched. The RIE etchant gas is chosen to attack tungsten and tungsten silicide more rapidly than it attacks silicon or silicon dioxide....