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Fault-Tolerant Sync Byte for Run-Length-Limited Codes

IP.com Disclosure Number: IPCOM000060975D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 4 page(s) / 46K

Publishing Venue

IBM

Related People

Bliss, WG: AUTHOR [+2]

Abstract

Data fields in magnetic recording are preceded by a "sync field" used to synchronize a phase-locked oscillator during readback. A special sync byte at the end of the sync field marks the start of data. Since the sync field, and especially the sync byte, are susceptible to errors which are not corrected by the data error correction code (ECC), there is a significant probability of loss of data due to errors in the sync area. This results in a failure to identify the sync byte or a failure by false detection at a time earlier than the proper time. This is especially true where higher density magnetic recordings, allowed by the use and dependence on ECC, puts even more stress on regions not covered by ECC. A system is therefore required to protect the sync area similar to the ECC protection of data.

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Fault-Tolerant Sync Byte for Run-Length-Limited Codes

Data fields in magnetic recording are preceded by a "sync field" used to synchronize a phase-locked oscillator during readback. A special sync byte at the end of the sync field marks the start of data. Since the sync field, and especially the sync byte, are susceptible to errors which are not corrected by the data error correction code (ECC), there is a significant probability of loss of data due to errors in the sync area. This results in a failure to identify the sync byte or a failure by false detection at a time earlier than the proper time. This is especially true where higher density magnetic recordings, allowed by the use and dependence on ECC, puts even more stress on regions not covered by ECC. A system is therefore required to protect the sync area similar to the ECC protection of data. The optimum sync field pattern in systems using run-length- limited (RLL) codes is one using all 3 length magnets (the shortest allowed). This provides the phase-locked oscillator with the optimum combination of timing information quality and quantity for both RLL(1,7) and RLL(2,7) codes. The sync byte and boundaries into both the sync field and into the data field are allowed only 3, 4 or 5 length magnets within the sync word because these are much less sensitive to extra bits than the longer magnets. The transitions between these lengths are also "stronger" than those between longer magnets because there is less bit shift by noise, off-track signals or defects. The intersymbol interference of these is minimized by restricting the variation of lengths. For the RLL(2,7) code, the restrictions are 3-3, 3-4, 4-4, 4-5, 5-5 and 5-longer. For the RLL(1,7) code, the previous are allowed and also 3-5. Since 3 is not the shortest magnet in RLL(1,7), a 3-5 is much less shift than a 3-5 would be in RLL(2,7). These restrictions keep the intersymbol interference bit shifts less than half the value of the worst-case data patterns. Fig. 1 shows RLL(1,7) and RLL(2,7) code patterns with the recognized combination of 1's shown in the 3, 7 and 12 positions of the sync byte detection shift register. Because the encoded pattern for both RLL(2,7) and RLL (1,7) codes is identical through the sync field and sync byte and particularly the sync byte detection region, the analysis and hardware can be identical. The principle of the fault-tolerant detection is a majority vote of 2 out of 3 of the transitions (ones) within the sync byte being present in the correct position. One of the three can be shifted or missing and identification of the sync byte is still possible. It is necessary to develop the correct pattern and hardware to eliminate all possible false candidates from the normal sync field and the transition into the sync byte or from patterns which may result from all the failure modes. The combinational logic derived for the sync byte decoder is: sync found = 5 .9 .10 .(6 .8) .(6+7+8) .[3 .7 .12+1(3 .7...