Browse Prior Art Database

High-Speed, Double-Dense SRAM and EEPROM Cell

IP.com Disclosure Number: IPCOM000060979D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Kauffmann, BA: AUTHOR [+4]

Abstract

This circuit provides a double-dense, high-speed static and non-volatile memory cell for maintaining data even during power loss.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

High-Speed, Double-Dense SRAM and EEPROM Cell

This circuit provides a double-dense, high-speed static and non-volatile memory cell for maintaining data even during power loss.

The circuit is a conventional six-device static random-access memory (SRAM) cell with an electrically erasable programmable read-only memory (EEPROM) cell as a shadow. The circuit incorporates isolation devices, appropriate load structures and dual electron injection structures (DEIS, see reference) to allow operation in any of three modes: 1) as a conventional six device SRAM cell, 2) as an EEPROM, without destroying SRAM data, and 3) as an EEPROM, and destroying SRAM data. In the figure, the following devices are added to the conventional six-device cell: transistors T3 and T4, which are the isolation devices, and DEIS structures D1 and D2. Load devices L are P-type cross- coupled or depletion loads. In circuit operation as a conventional SRAM, with array high voltage V2 = Vdd, the control gate signal CG is held high at Vdd. Floating gates FG1 and FG2 are capacitively coupled such that the surface underneath is inverted and normal SRAM read and write (I/O) operation can take place. Alternatively, as an SRAM with V2 = Vdd/2, the power factor CV2 in the array is greatly reduced without substantial change in performance by precharging bit lines BL and BLN to Vdd/2. For circuit operation as an EEPROM, without destroying SRAM data, CG is grounded and V2 is brought to Vdd/2. Worst-case conditions are found while trying to read a non-volatile '0' with a static '1' behind it at Vdd/2. In this situation, FG1 has a non-volatile '0' stored on it; FG2 has a non-volatile '1' stored on it; node A contains a SRAM '1' at Vdd/2 and node B contains a SRAM '0' at ground. Bit lines BL and BLN are precharged to Vdd. With CG at ground, and with the appropriate c...