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Improved Lateral PNP With Polysilicon Contacts

IP.com Disclosure Number: IPCOM000060981D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Fitzpatrick, DA: AUTHOR [+3]

Abstract

A method has been proposed to improve the lateral PNP (LPNP) in semiconductor devices by forming small PNP emitters by image transfer from a sidewall. The narrow width of the smaller emitter and self-aligned contact reduces series emitter resistance. Beta characteristics also are significantly improved. The invention calls for changes in a conventional bipolar manufacturing process following a 450 L/square resistor implant step as follows: a. Blanket LPCVD (low pressure chemical vapor deposition) nitride 800ŒC, 100 nm thick. b. Photoresist (PR), 2 m thick, patterned with LPNP mask #1. Plasma harden the resist. c. Blanket plasma oxide, 0.6 m thick, 245ŒC. d. Blanket RIE (reactive ion etch) plasma oxide, 0.6 m, end point detect on the underlying nitride layer and overetch slightly.

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Improved Lateral PNP With Polysilicon Contacts

A method has been proposed to improve the lateral PNP (LPNP) in semiconductor devices by forming small PNP emitters by image transfer from a sidewall. The narrow width of the smaller emitter and self-aligned contact reduces series emitter resistance. Beta characteristics also are significantly improved. The invention calls for changes in a conventional bipolar manufacturing process following a 450 L/square resistor implant step as follows:
a. Blanket LPCVD (low pressure chemical vapor deposition) nitride 800OEC, 100 nm thick. b. Photoresist (PR), 2 m thick, patterned with LPNP mask #1. Plasma harden the resist. c. Blanket plasma oxide, 0.6 m thick, 245OEC. d. Blanket RIE (reactive ion etch) plasma oxide, 0.6 m, end point detect on the underlying nitride layer and overetch slightly. At this juncture, all of the vertical surfaces of the PR openings will be lined with 0.6 m thick walls of plasma oxide "studs" (Fig. 1). e. Apply a second coat of PR to fill the windows and present a flat top surface. Bake the resist. f. PR, 2 m thick, patterned with LPNP mask #2 to open windows for removing unwanted studs. g. RIE to remove unwanted studs, end point detect on the under lying nitride. Do not overetch. Strip PR. h. PR, 2 m thick. Blanket RIE the PR to expose the top portion of the studs. RIE the exposed studs (Fig. 2). i. Continue to RIE the exposed nitride and oxide layers with BHF (buffered hydrofluoric acid), dip etch to complete removal of the oxide. Strip PR, preclean and diffuse phosphorous for N-base regions, if desired (Fig. 3). j. Revert to the normal process to open the NPN base region and deposit polysilicon (Fig. 4). k. Cont...