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CMOS Supply Sequence Circuit

IP.com Disclosure Number: IPCOM000061003D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Penoyer, RF: AUTHOR

Abstract

A circuit is described which assures that complementary metal oxide semiconductor (CMOS) n-wells are sufficiently biased relative to p- channel source/drains to prevent forward biasing of junctions. The circuit shown in Fig. 1 operates (with typical voltage levels of: high supply voltage (VH) = 5 volts, n-well supply voltage (Vnw) = 6 volts, substrate supply voltage (Vsub) = -1 volt; and threshold voltage of n- channel transistors (VTn) = 1 volt @ source-to-substrate voltage (Vs-sub) = -1 volt and VTn = 1.7 volts @ Vs-sub = -6 volts) as follows: 1. VH and Vnw supplies come up, charging n-well bus Nwb through the impedance Z of the Vnw supply and high supply bus VHb through the source follower, transistor N1. Transistor N1 maintains on VHb a voltage of one VT below the n-well bus potential. 2.

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CMOS Supply Sequence Circuit

A circuit is described which assures that complementary metal oxide semiconductor (CMOS) n-wells are sufficiently biased relative to p- channel source/drains to prevent forward biasing of junctions. The circuit shown in Fig. 1 operates (with typical voltage levels of: high supply voltage (VH) = 5 volts, n-well supply voltage (Vnw) = 6 volts, substrate supply voltage (Vsub) = -1 volt; and threshold voltage of n- channel transistors (VTn) = 1 volt @ source-to-substrate voltage (Vs-sub) = -1 volt and VTn = 1.7 volts @ Vs-sub = -6 volts) as follows: 1. VH and Vnw supplies come up, charging n-well bus Nwb through the impedance Z of the Vnw supply and high supply bus VHb through the source follower, transistor N1. Transistor N1 maintains on VHb a voltage of one VT below the n- well bus potential. 2. Transistor P1 charges the gate of transistor P2 to VH while the potential across the resistive divider R1 and R2 is less than VT of transistor N2. 3. When the potential of VHb is sufficiently high that the gate potential of transistor N2 reaches VT, the gate of transistor P2 is discharged, causing transistor P2 to charge VHb to a full VH level. 4. To assure that the n-well bus potential exceeds the VH bus potential at the time transistor P2 is turned on, the resistive divider R1 and R2 is proportioned to produce a voltage equal to VT of transistor N2 when the n-well bus potential is above VH. Fig. 2 shows typical circuit operation potentials whe...