Browse Prior Art Database

High Performance Interprocessor Communications

IP.com Disclosure Number: IPCOM000061005D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Treiber, RK: AUTHOR

Abstract

This article describes a method for transferring data between two IBM System/370 XA processors utilizing Channel-To-Channel Adapter (CTCA) facilities that implement the PREPARE command. A variant of this technique could be used on a non-XA System/370 processor with the Suspend and Resume I/O feature. The read side channel program causes a maximum of one intermediate status Program Controlled Interrupt (PCI) per read operation to inform the processor that one or more read operations have completed. The write side channel program causes 1/N PCI intermediate status interrupts per write operation by setting the PCI flag on in every Nth channel program section, where N typically equals 2, but can be any integer.

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High Performance Interprocessor Communications

This article describes a method for transferring data between two IBM System/370 XA processors utilizing Channel-To-Channel Adapter (CTCA) facilities that implement the PREPARE command. A variant of this technique could be used on a non-XA System/370 processor with the Suspend and Resume I/O feature. The read side channel program causes a maximum of one intermediate status Program Controlled Interrupt (PCI) per read operation to inform the processor that one or more read operations have completed. The write side channel program causes 1/N PCI intermediate status interrupts per write operation by setting the PCI flag on in every Nth channel program section, where N typically equals 2, but can be any integer. The write side interrupt informs the processor that write operations associated with the channel program sections prior to the one active at time of interrupt have completed. Channel programs for high performance communications according to this method are shown in the figure. Each Channel Command Word (CCW) in the channel program command chains to another CCW; thus the channel never presents final status interrupt to the processor. A channel program section is associated with each buffer (or set of buffers related via Indirect Address Words (IDAW)). On the write side of the CTCA, the execution of a channel program is suspended using the suspend bit in a NO-OP CCW any time there are no additional buffers to send. When the write side I/O operation is initiated, suspend interrupts are disabled so that no suspend interrupt occurs even when there is nothing to transfer. Each time a new buffer is ready to be sent, the channel program section for the new buffer is chained onto the prior channel program by replacing the NO-OP/suspend CCW with a TIC (transfer in channel) CCW that transfers channel operation to the CCWs associated with the new buffer and then issuing a Resume Subchannel instruction (RSCH). If the subchannel had not proces...