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Inhibit Sequencing Delay Circuit

IP.com Disclosure Number: IPCOM000061018D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Kiesling, DA: AUTHOR [+2]

Abstract

Electrical noise created during VLSI chip testing may be controlled by keeping off-chip drivers inhibited until applied conditions of test are completed. The drivers are then 'enabled' in groups, with a sequencing delay between groups, to take a test measurement. This is followed by the drivers being inhibited in groups with a sequencing delay between groups. This article discloses a circuit for providing significant delay, utilizing a small area on the VLSI chip, for the purpose of off-chip driver 'inhibit' and 'enable' sequencing. The delayed inverter circuit shown in Fig. 1 is organized into a sequencing network providing symmetrical sequencing delays for 'inhibit'/'enable' functions and requires only a single 'inhibit' input chip pad.

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Inhibit Sequencing Delay Circuit

Electrical noise created during VLSI chip testing may be controlled by keeping off-chip drivers inhibited until applied conditions of test are completed. The drivers are then 'enabled' in groups, with a sequencing delay between groups, to take a test measurement. This is followed by the drivers being inhibited in groups with a sequencing delay between groups. This article discloses a circuit for providing significant delay, utilizing a small area on the VLSI chip, for the purpose of off-chip driver 'inhibit' and 'enable' sequencing. The delayed inverter circuit shown in Fig. 1 is organized into a sequencing network providing symmetrical sequencing delays for 'inhibit'/'enable' functions and requires only a single 'inhibit' input chip pad. It is designed with a N 15 nsec delay per inverter so that 6 inverters can be chained to give a 'one-stage' delay of N 90 nsec. This implementation allows N 90 nsec delay between each group of drivers being either 'inhibited' or 'enabled'. The small delay segment of the inverter (N 15 nsec) allows flexibility in design of the stage delay, i.e., 12 inverters will give 180 nsec of stage delay. The delayed inverter circuit shown in Fig. 1 is a diode transistor logic (DTL) circuit using an input Low Barrier Schottky Barrier Diode (LBSBD) and an advanced design transistor operating in inverse mode with no clamping thus allowing the transistor to saturate. A single high value base resistor Rb is used i...