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Field-Defined Bipolar Structure in CMOS Technology

IP.com Disclosure Number: IPCOM000061022D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

El-Kareh, B: AUTHOR

Abstract

This article features a technique for incorporating a bipolar device into a CMOS structure without additional masks or processing steps. In special integrated circuit applications, e.g., receivers, interface circuits and analog designs, it is often desirable to incorporate bipolar structures in CMOS technology. A method for fabricating vertical npn and lateral pnp bipolar transistors without additional steps is described. Fig. 1 shows a P-substrate 10 with an N-well 11 and a layer of nitride 12 which has been reactive ion etched (RIE) through a thin photoresist mask 13 to define recessed oxide (ROX) isolation regions. After removal of the nitride layer 12 from the ROX windows 14, the bipolar devices will be integrated into the N-well. All process steps to this point are conventional CMOS processes. Fig.

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Field-Defined Bipolar Structure in CMOS Technology

This article features a technique for incorporating a bipolar device into a CMOS structure without additional masks or processing steps. In special integrated circuit applications, e.g., receivers, interface circuits and analog designs, it is often desirable to incorporate bipolar structures in CMOS technology. A method for fabricating vertical npn and lateral pnp bipolar transistors without additional steps is described. Fig. 1 shows a P-substrate 10 with an N-well 11 and a layer of nitride 12 which has been reactive ion etched (RIE) through a thin photoresist mask 13 to define recessed oxide (ROX) isolation regions. After removal of the nitride layer 12 from the ROX windows 14, the bipolar devices will be integrated into the N-well. All process steps to this point are conventional CMOS processes. Fig. 2 shows a second and thicker resist layer 15 which is deposited on top of the thin first resist layer 13 after the first resist layer is hardened. To incorporate bipolar devices into the CMOS process, the second resist mask 15 allows boron to be implanted into some regions of the N-well 11. In general, resist mask 15 defines the CMOS field tailor I/I regions. The mask is also used to define the base region of the vertical bipolar npn transistor 16 and the emitter/ collector region of the lateral bipolar pnp transistor 17. The boron is implanted at the CMOS-defined dose. A slightly higher implant energy is used so...