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Complementary Diode Logic

IP.com Disclosure Number: IPCOM000061045D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Montegari, F: AUTHOR

Abstract

This article describes the use of high capacitance diodes and a complementary NPN-PNP inverter to produce a high speed, low power logic circuit. High transient base current must be provided to the base of a bipolar transistor if a fast transition between logic states is to be achieved at its collector, but after the transition has completed, base current should be reduced to the minimum amount necessary to retain the new state. This is accomplished in the complementary diode logic (CDL) circuit by coupling the input transition into and out of the inverter bases through diodes having high shunt capacitance, and then retaining the logic state with high value resistors. The diodes also serve as logic gates. The CDL NAND and NOR circuits shown in Figs.

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Complementary Diode Logic

This article describes the use of high capacitance diodes and a complementary NPN-PNP inverter to produce a high speed, low power logic circuit. High transient base current must be provided to the base of a bipolar transistor if a fast transition between logic states is to be achieved at its collector, but after the transition has completed, base current should be reduced to the minimum amount necessary to retain the new state. This is accomplished in the complementary diode logic (CDL) circuit by coupling the input transition into and out of the inverter bases through diodes having high shunt capacitance, and then retaining the logic state with high value resistors. The diodes also serve as logic gates. The CDL NAND and NOR circuits shown in Figs. 1 and 2, respectively, use high capacitance base-collector diodes to couple an input transition into a complementary bipolar inverter. Starting with both inputs 1 and 2 of Fig. 1 at a down level, current flows from Vcc through the emitter-base of transistor T1, then through diode D4, resistor R1, and both diodes D5 and D6 to the down level at input nodes 1 and 2. Current also flows from Vcc through the emitter-base of T1, then through diode D3, resistor R2 and both D5 and D6 to the down level at input nodes 1 and 2. Current flowing through the emitter-base of T1 holds T1 on while the same current flowing through D5 and D6 produces a level at node C that will not turn transistor T2 on. Both D1 and D2 are reverse biased. Both input nodes provide the same function, but circuit operation will be described by following current flow as one node changes state. When input node 1 goes up and node 2 remains down, D5 becomes reverse biased and current flows from input node 1 through D2, R1 and D6 into input node 2 D4 also becomes reverse biased. When input node 1 is already up and node 2 goes up, the transition is passed from node 2, through the high diffusion capacitance of D6, into node C, then through diode D7, and into the base-emitter of T2 to ground, tu...