Browse Prior Art Database

Video Overlay Synchronizer/Sync Generator

IP.com Disclosure Number: IPCOM000061053D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Ogle, ST: AUTHOR

Abstract

This article describes a circuit arrangement that generates the proper horizontal and vertical sync signals for video controllers that can both overlay text on an external video signal and generate video output when no external video source is available. In designing video circuits that can both overlay text on an external video input and also generate video output when no external video source is available, the following two cases must be supported: 1. Video Source Synchronization - In this case the sync signals used to generate the overlay video must be synchronous with the sync signals of the external source. 2. Sync Generation - Sync signals for generating the video must be created even when there are no external sync signals available.

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Video Overlay Synchronizer/Sync Generator

This article describes a circuit arrangement that generates the proper horizontal and vertical sync signals for video controllers that can both overlay text on an external video signal and generate video output when no external video source is available. In designing video circuits that can both overlay text on an external video input and also generate video output when no external video source is available, the following two cases must be supported: 1. Video Source Synchronization - In this case the sync signals used to generate the overlay video must be synchronous with the sync signals of the external source. 2. Sync Generation - Sync signals for generating the video must be created even when there are no external sync signals available. In the first case, the effects of the sync generating circuitry on the period and pulse width of the external source pulses must be minimized, allowing the recreated sync signal to be as close as possible to the incoming sync signal. In the second case, the sync signals that are created must have periods and pulse widths acceptable for use in present- day monitors. The circuit arrangement of this disclosure is shown in block diagram in the drawing. The parameters used in this circuit are an input clock frequency F, an external sync input frequency H and an optimum pulse width W. The number of counter bits required, M, is equal to log2(H) . The decoder value for decode logic 1, A, equals FxW. The decoder value for decode logic 2, B, is equal to H x 1.05. In describing the operation of this circuit Hsync will be used although Vsync could just as easily be chosen. The pulse output of the pulse- on-edge circuit should be as short as possible while ensuring that the counter...