Browse Prior Art Database

High Speed, High Sensitivity Comparator

IP.com Disclosure Number: IPCOM000061058D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Czarniak, JC: AUTHOR [+2]

Abstract

This is a high speed high sensitivity CMOS comparator which improves upon the comparator described by Andrew G. F. Dingwall, et al at the ISSCC85, February 13, 1985. The improved comparator (Fig. 1) includes two inverter stages, two capacitors C1 and C2 and five switches S1, S2, S3, S4 and S5. The comparator operates in a regenerative mode and thus needs two phases: a first phase of initialization during which Vref is sampled in C1 and each inverter stage is set to its quiescent voltage point, and a second phase (comparison phase) during which the analog input is compared to the reference. The clocking diagram is shown in Fig. 2. The four clocks ×1 through ×4 are identical: i.e., they have the same period and the same rise and fall time.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

High Speed, High Sensitivity Comparator

This is a high speed high sensitivity CMOS comparator which improves upon the comparator described by Andrew G. F. Dingwall, et al at the ISSCC85, February 13, 1985. The improved comparator (Fig. 1) includes two inverter stages, two capacitors C1 and C2 and five switches S1, S2, S3, S4 and S5. The comparator operates in a regenerative mode and thus needs two phases: a first phase of initialization during which Vref is sampled in C1 and each inverter stage is set to its quiescent voltage point, and a second phase (comparison phase) during which the analog input is compared to the reference. The clocking diagram is shown in Fig. 2. The four clocks ×1 through ×4 are identical: i.e., they have the same period and the same rise and fall time. But ×2 is delayed interval Tr2 with respect to ×1, ×3 is delayed internal Tr3, and ×4 internal Tr4. The comparison is made in five successive steps and lasts one period of T1. -Step 1: S1, S2 and S5 are closed; S3 and S4 are open. This is an autozeroing step during which Vref is sampled into C1 and each inverter is set to its quiescent voltage point. -Step 2: S1 and S5 are closed; S3, S2 and S4 are open. S2 opens while S1 and S5 remain closed. The feed-through introduced by the opening of S2 is integrated in C1 and C2. To insure a good integration of this feed-through charge, C1 and C2 must be connected to a low impedance point. Thus, S1 and S5 should remain closed while S2 opens. -Step 3: S1 is open, while S3 is closed. S5 and S4 re...