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Self-Test for Reconfigurable Pipeline Neighborhood Processor

IP.com Disclosure Number: IPCOM000061070D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Kimmel, MJ: AUTHOR [+2]

Abstract

Reconfigurability of a processor made up of a number of neighborhood processing elements facilitates fault detection and fault bypass, using pseudoduplication to detect a fault by comparing results of performing the same function with different processor configurations, and using a voting technique to determine and bypass the fault location. A reconfigurable pipelined image processor can assume a number of configurations by variably connecting neighborhood transformation processing elements, boolean combiners (BC) and enumerators (EN) which provide outputs as timed X, Y coordinate pairs. An operation flow graph might, for example, be defined as G in Fig. 1. One can then define (and implement through software) a self-checking network G', as shown in Fig.

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Self-Test for Reconfigurable Pipeline Neighborhood Processor

Reconfigurability of a processor made up of a number of neighborhood processing elements facilitates fault detection and fault bypass, using pseudoduplication to detect a fault by comparing results of performing the same function with different processor configurations, and using a voting technique to determine and bypass the fault location. A reconfigurable pipelined image processor can assume a number of configurations by variably connecting neighborhood transformation processing elements, boolean combiners (BC) and enumerators (EN) which provide outputs as timed X, Y coordinate pairs. An operation flow graph might, for example, be defined as G in Fig. 1. One can then define (and implement through software) a self-checking network G', as shown in Fig. 2, where: G" is a copy of G XOR is a BC programmed to the logical exclusive-OR function. If the network functions as a reconfigurable pipeline neighborhood processor, with outputs provided as timed X, Y coordinates by an enumerator, a running comparison of duplicate subgraphs results within the capability of the enumerator. In this operation flow graph, the output of G' is identical to that of G (provided that the internal G and G" subgraphs are functioning correctly). When one of the internal G and G" subgraphs malfunctions to produce incorrect results, the enumerator EN interrupts the host processor with an (XY) coordinate, indicating the point at whic...