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Contactless Testable Latches

IP.com Disclosure Number: IPCOM000061074D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Chiu, GL: AUTHOR

Abstract

Shift register latches are used to turn sequential logic testing into combinatorial logic testing because sequential logic is too difficult to test. Level Sensitive Scan Design (LSSD) has been adopted partly because of this reason, but LSSD pays a penalty in real estate. It doubles the size of a latch and it needs A and B clocks for shifting. The overall cost of real estate using LSSD is typically 15 to 25%. A contactless testable latch is described herein that can achieve the same function as a shift register latch using E-beam or laser testers. Its real estate requirement is far less compared to the LSSD approach. The drawing shows the logic circuit diagram of this new latch.

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Contactless Testable Latches

Shift register latches are used to turn sequential logic testing into combinatorial logic testing because sequential logic is too difficult to test. Level Sensitive Scan Design (LSSD) has been adopted partly because of this reason, but LSSD pays a penalty in real estate. It doubles the size of a latch and it needs A and B clocks for shifting. The overall cost of real estate using LSSD is typically 15 to 25%. A contactless testable latch is described herein that can achieve the same function as a shift register latch using E-beam or laser testers. Its real estate requirement is far less compared to the LSSD approach. The drawing shows the logic circuit diagram of this new latch. The latch itself is fed by a multiplexer which multiplexes the latch to operate in either the system mode during normal operation or test mode during testing. During system mode, the test control signal blocks the test system data input. During test mode, the system control signal blocks the system data input. The test data input can be set to low or high, depending on whether the diode is illuminated by the E-beam/laser or not. The electron beam or the optical beam can pull the test input node to low via the beam-induced current. The software test program controls whether the beam will hit a diode or not according to the test pattern. Thus, every register can be set to 0 or 1 using neither shifting hardware nor A, B clocks. The only requirement in this approac...