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PROCESS FOR IMPROVING SiO2-Si INTERFACE PROPERTIES

IP.com Disclosure Number: IPCOM000061082D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Nguyen, TN: AUTHOR [+2]

Abstract

Low temperature processing is required in the fabrication of VLSI circuits to minimize the diffusion and redistribution of dopants to obtain shallow and controllable impurity profiles. It is particularly important when dopants in such critical regions as the channel, source and drain of MOS transistors are already in place. The reduced temperature cycles, however, can result in high oxide fixed charge and interface trap charge due to inadequate annealing of the gate oxide. These charges are known to depend only on the last temperature cycle; thus, a high temperature anneal following the gate oxidation will not be effective.

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PROCESS FOR IMPROVING SiO2-Si INTERFACE PROPERTIES

Low temperature processing is required in the fabrication of VLSI circuits to minimize the diffusion and redistribution of dopants to obtain shallow and controllable impurity profiles. It is particularly important when dopants in such critical regions as the channel, source and drain of MOS transistors are already in place. The reduced temperature cycles, however, can result in high oxide fixed charge and interface trap charge due to inadequate annealing of the gate oxide. These charges are known to depend only on the last temperature cycle; thus, a high temperature anneal following the gate oxidation will not be effective. Their values must be minimized because they degrade transistor performances by reducing the threshold voltage and surface mobility, changing the I-V characteristics, and increasing the subthreshold leakage current and surface recombination. In this article a process is described for improving the properties of the SiO2-Si interface without disturbing the dopant distributions in the silicon substrate significantly. Thermal oxide was grown on 3.25" <100> 2 ohm-cm P- type silicon wafers to about 100 ~ thickness. Some wafers were annealed in Ar ambient at temperatures from 1000 to 1150OEC for varying times between 5 and 60 seconds in a heat pulse system. Some wafers were subjected to a furnace anneal at 900OEC for 30 minutes also in Ar ambient. Capacitors were fabricated by evaporating aluminum through 32- and 60-mil diameter dot shadow mask; high-frequency and quasi-static C-V measurements were performed to determine the flatband voltage (Vfb), oxide fixed charge density (Nf), and interface trap charge density at mid-...