Browse Prior Art Database

LSSD Clock Generation Using Fundamental Mode Circuits

IP.com Disclosure Number: IPCOM000061085D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Donaldson, JE: AUTHOR [+4]

Abstract

Normally fundamental mode circuits and level sensitive scan design (LSSD) circuits are incompatible because one edge is sensitive and the other is level sensitive. Compatibility is achieved by placing the LSSD latch circuit in the feedback path of the fundamental mode circuit. The LSSD latch in the feedback path facilitates testing of the circuit in an LSSD environment, such as described in U. S. Patent 4,268,902. When not in the test mode, i.e., during normal operation of the circuit, the fundamental mode circuit functions in its normal manner and the LSSD latch acts as a delay as the test clocks are held active. Many types of circuits such as state machines, etc., can take advantage of this combination, and a particular implementation for a clock generator is shown in Figs. 1 and 2.

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LSSD Clock Generation Using Fundamental Mode Circuits

Normally fundamental mode circuits and level sensitive scan design (LSSD) circuits are incompatible because one edge is sensitive and the other is level sensitive. Compatibility is achieved by placing the LSSD latch circuit in the feedback path of the fundamental mode circuit. The LSSD latch in the feedback path facilitates testing of the circuit in an LSSD environment, such as described in U. S. Patent 4,268,902. When not in the test mode, i.e., during normal operation of the circuit, the fundamental mode circuit functions in its normal manner and the LSSD latch acts as a delay as the test clocks are held active. Many types of circuits such as state machines, etc., can take advantage of this combination, and a particular implementation for a clock generator is shown in Figs. 1 and 2. Thus the speed of the fundamental mode circuit is combined with the testability of LSSD circuits. Whether or not the delay of the LSSD circuit enters into the speed of the fundamental mode circuit depends upon the technology in which the fundamental mode circuit is implemented. A LSSD fundamental mode clock generator is shown schematically in Fig. 1, and is a divide by N implementation, where N=3. The input includes both phases of an oscillator, and the necessary LSSD controls. The output is a square-wave output at 1/3 the frequency, and three non-overlapping clocks, each at three times the period of the input. Note that the choice of outputs is not restricted to this example (Fig. 4). The name "fundamental mode" refers to the unclocked nature of the circuit consisting of combinatorial logic blocks with feedback, thus forming a machine of multiple states. This circuit configuration is generally faster than an equivalent clocked implementation. A drawback of the fundamental mode circuit is the difficulty with which it may be tested. By merging the best of the fundamental mode characteristics with the testable nature of LSSD, the resulting circuit is clocked by the LSSD clocks only when appropriate for testing, and during functional use these same clocks are held in a non-controlling state, as in Fig. 2. In the design of fundamental mode circuits it is important that single input changes be made to the circuit and a stability state achieved prior to the next input change. In this example both phases of the input oscillator are required to switch simultaneously. If path delays from one state to the next and/or the skew between the two phases of the oscillator cannot be held to a tolerance, then redundant decodes will be required to prevent output glitches and/or missing states. Careful control of the path delay and the source of the oscillator will eliminate most problems. A state table is defined so that a state transition will occur on each change of the input oscillator. The transition between any two adjacent states must be limited to a single-state variable change (Fig. 3). Unused states must gr...