Browse Prior Art Database

Loading Device Channel Address Via Scan Ring

IP.com Disclosure Number: IPCOM000061086D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Kuhlman, CL: AUTHOR [+3]

Abstract

Common I/O processor cards are used to minimize design effort for attaching new devices. A read-only storage (ROS) is added to the processor card and contains Initial Program Load (IPL) and diagnostic code, but does not contain a device channel address hardcoded. The device channel address is loaded by scanning a hardware register through a level sensitive scan design (LSSD) service control adapter interface. In the figure, an I/O processor card 10 is connected by busses to a CPU 12 and a system control adapter 14. Other I/O attachments 16 and 18 are also connected to these busses. Previous implementations of common I/O processor cards provided a device channel address register that the I/O processor could write under microcode control.

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Loading Device Channel Address Via Scan Ring

Common I/O processor cards are used to minimize design effort for attaching new devices. A read-only storage (ROS) is added to the processor card and contains Initial Program Load (IPL) and diagnostic code, but does not contain a device channel address hardcoded. The device channel address is loaded by scanning a hardware register through a level sensitive scan design (LSSD) service control adapter interface. In the figure, an I/O processor card 10 is connected by busses to a CPU 12 and a system control adapter 14. Other I/O attachments 16 and 18 are also connected to these busses. Previous implementations of common I/O processor cards provided a device channel address register that the I/O processor could write under microcode control. The value for the device channel address had to be hardcoded in the microcode, thus making it impossible for different I/O attachments to share initialization microcode. As a result, microcode was provided in one of two different approaches, both of which had their shortcomings. In one approach, a ROS on a separate adapter card is personalized for the I/O device. This created a problem in that microcode was contained on one card, but executed on another, making error location determination difficult. Another approach was to have random- access memory (RAM) on the processor card loadable via a scan path with extra support hardware. The number of scans required to load the code for IPL an...