Browse Prior Art Database

Power Sequence Independent Expansion Bus Interface

IP.com Disclosure Number: IPCOM000061090D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Dang, LQ: AUTHOR [+3]

Abstract

Computer systems may expand or add auxiliary hardware by connecting an external unit to the host system. In systems where the external unit is directly attached to the host system's I/O bus, faults in the expansion unit may propagate to the host system, making the host system inoperative. A circuit is provided which logically disconnects the external bus in the external I/O unit from the local bus in the host system when either a host system reset or an I/O unit power fault occurs. The host may also disconnect from the external bus under program control. Facilities are provided which allow the host system to test the state of the external bus lines. The drawing is a diagram of the expansion bus interface. The output of latch 2 on I/O Reset line 17 controls gate 3 and provides a reset signal to the external unit.

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Power Sequence Independent Expansion Bus Interface

Computer systems may expand or add auxiliary hardware by connecting an external unit to the host system. In systems where the external unit is directly attached to the host system's I/O bus, faults in the expansion unit may propagate to the host system, making the host system inoperative. A circuit is provided which logically disconnects the external bus in the external I/O unit from the local bus in the host system when either a host system reset or an I/O unit power fault occurs. The host may also disconnect from the external bus under program control. Facilities are provided which allow the host system to test the state of the external bus lines. The drawing is a diagram of the expansion bus interface. The output of latch 2 on I/O Reset line 17 controls gate 3 and provides a reset signal to the external unit. When the I/O reset signal on line 17 is asserted, gate 3 is turned off, isolating external bus 18 from local bus 13. The reset state of latch 2 causes the I/O reset on line 17 to turn on. The reset input to latch 2 is the OR of two hardware- controlled signals, I/O power fault on line 16 and host reset on line 10, and one software controlled signal, software reset on line 11. This circuit insures that the external bus 18 is isolated from the local bus 13 for the three reset conditions of latch 2. The host reset condition prevents faults on the external bus 18 at power-on time from causing errors in the host system...