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Read, Read/Write Memory Cell

IP.com Disclosure Number: IPCOM000061093D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Smith, CD: AUTHOR

Abstract

A bipolar dual-port random-access memory (RAM) cell design can integrate devices across memory cell boundaries. As seen in the schematic, the RAM has two ports, one port being read port and the other a read/write port. Word Line Read (WLR) and Word Line Read/Write (WLR/W) are the cell inputs for ports read and read/write, J is the cell current bias input, and bit read (BR) and bit read not (BRN) are current sinking bit line outputs that represent the read port's true and complement outputs. Bit read/write (BRW) and bit read/write not (BRWN) are the source currents for the bit lines that represent the read/write port's true and complement input/output. The Word line inputs and the bias input for the cells in an array are each wired in rows, the number of cells per row being the number of bits per word.

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Read, Read/Write Memory Cell

A bipolar dual-port random-access memory (RAM) cell design can integrate devices across memory cell boundaries. As seen in the schematic, the RAM has two ports, one port being read port and the other a read/write port. Word Line Read (WLR) and Word Line Read/Write (WLR/W) are the cell inputs for ports read and read/write, J is the cell current bias input, and bit read (BR) and bit read not (BRN) are current sinking bit line outputs that represent the read port's true and complement outputs. Bit read/write (BRW) and bit read/write not (BRWN) are the source currents for the bit lines that represent the read/write port's true and complement input/output. The Word line inputs and the bias input for the cells in an array are each wired in rows, the number of cells per row being the number of bits per word. The bit lines for the array cell's outputs are each wired in columns. The number of cells per column is the number of words per array. T1 and T2 are PNP transistors, T3, T4, T5 and T6 are NPN transistors, and X1 and X2 are Schottky barrier diodes. R1 is a resistor. Devices T1, T3 and X1 are put in one isolation region, devices T2, T4 and X2 are put in another isolation region, and devices T5, T6 and R1 are effectively put in their own isolation region. They are effectively in the same isolation region, as one cell's T5 may be integrated with T5 of the next cell in the column, etc. The same integration applies to T6. In addition, R1 would...