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Improved Systems Timing Using a Pseudo-Edge-Triggered Shift Register Latch

IP.com Disclosure Number: IPCOM000061095D
Original Publication Date: 1986-Jun-01
Included in the Prior Art Database: 2005-Mar-09
Document File: 3 page(s) / 51K

Publishing Venue

IBM

Related People

Jeremiah, TL: AUTHOR [+3]

Abstract

In a conventional level sensitive scan design (LSSD) having a latch- trigger design, L1 latches feed directly into L2 latches. The L2's feed combinatorial logic, which then feeds the L1's. Often, the L1 is fed directly from its own L2 for the purpose of holding data in a pipeline structure. In a purely hazard-free design, the L1's and L2's would be fed by independent non-overlapping clocks. This creates a severe timing penalty because pulse cycles must be adjusted to account for late data arriving from the longest combinatorial path. Failure to do this would cause wrong data to the L1's to be latched because the data in a long path could arrive at the latch after its clock has become inactive. In high performance designs, the L1, L2 clocks are overlapped.

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Improved Systems Timing Using a Pseudo-Edge-Triggered Shift Register Latch

In a conventional level sensitive scan design (LSSD) having a latch- trigger design, L1 latches feed directly into L2 latches. The L2's feed combinatorial logic, which then feeds the L1's. Often, the L1 is fed directly from its own L2 for the purpose of holding data in a pipeline structure. In a purely hazard-free design, the L1's and L2's would be fed by independent non-overlapping clocks. This creates a severe timing penalty because pulse cycles must be adjusted to account for late data arriving from the longest combinatorial path. Failure to do this would cause wrong data to the L1's to be latched because the data in a long path could arrive at the latch after its clock has become inactive. In high performance designs, the L1, L2 clocks are overlapped. This optimizes machine cycle time but introduces another timing constraint. In this case, to prevent latches from changing values unintentionally (data early), extra delay or padding must be included in the shorter logic paths. This padding requirement is particularly evident where L2's feed L1's directly with no intervening logic. Clock distribution is further complicated by circuit delay tolerances which result in clock skew and pulse shrinkage which must be accounted for in the design. In Fig. 1, a modified L1/L2 structure is defined logically. The L1's feed directly into the L2's. The L2's also feed combinatorial logic which then feeds L1's. For this design, logically and electrically, the L1 and L2 are fed by the same system clock; likewise, the L1 is clocked with the positive phase of this clock and the L2 by the negative polarity of the system clock. These "two" clocks have the same physical net. In Fig. 1 at T0, the L1's are activated by the positive system clock and the L2 clock gating is disabled. At T1, the converse occurs and data transfer is accomplished to the L2. At T2, the cycle repeats itself. This in effect emulates an edge-triggered latch pair which in reality is made of two DC stable latches. Likewise, since both latches are fed by the same clock, skewing problems are minimized. No padding is required when an L2 directly feeds its own L1 since the same clock feeds both latches. Also, since non-overlapping clocks are not required, the amount of time available for the long path logic is increased without suffering a proportional increase in machine cycle time. The system clock is A...